JPS5687201A - Muting circuit of record player - Google Patents

Muting circuit of record player

Info

Publication number
JPS5687201A
JPS5687201A JP16155579A JP16155579A JPS5687201A JP S5687201 A JPS5687201 A JP S5687201A JP 16155579 A JP16155579 A JP 16155579A JP 16155579 A JP16155579 A JP 16155579A JP S5687201 A JPS5687201 A JP S5687201A
Authority
JP
Japan
Prior art keywords
circuit
nand circuit
nand
output
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16155579A
Other languages
Japanese (ja)
Inventor
Tadao Betsumiya
Yasuhiro Ishigaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16155579A priority Critical patent/JPS5687201A/en
Publication of JPS5687201A publication Critical patent/JPS5687201A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To suppress induced noises and vibrations even when a control motor is rotated continuously in the muting circuit of a record player.
CONSTITUTION: When a positive signal is inputted to input terminal 1 of NAND circuit 2, control motor 7 continues to rotate until key top 24 enters groove 31 of cam 20. Then, NAND circuit 3 and NAND circuit 21 constitute a monostable circuit and as NAND circuit 3 generates a high-level output, NAND circuit 8 and 9 are put into operation to short-circuit output terminals 16W19 of a pickup, providing muting operation. As the output of NAND circuit 3 changes from the high level to the low level, the monostable circuit consisting of NAND circuits 10 and 13, resistance 12 and capacitor 11 operate to generate a high-level output, providing muting operation. The time constant determined by resistance 12 and capacitor 11 provides a time longer than that of the single rotation of cam 20.
COPYRIGHT: (C)1981,JPO&Japio
JP16155579A 1979-12-14 1979-12-14 Muting circuit of record player Pending JPS5687201A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16155579A JPS5687201A (en) 1979-12-14 1979-12-14 Muting circuit of record player

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16155579A JPS5687201A (en) 1979-12-14 1979-12-14 Muting circuit of record player

Publications (1)

Publication Number Publication Date
JPS5687201A true JPS5687201A (en) 1981-07-15

Family

ID=15737328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16155579A Pending JPS5687201A (en) 1979-12-14 1979-12-14 Muting circuit of record player

Country Status (1)

Country Link
JP (1) JPS5687201A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58105453A (en) * 1981-12-16 1983-06-23 Sony Corp Record player

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58105453A (en) * 1981-12-16 1983-06-23 Sony Corp Record player
JPH0462147B2 (en) * 1981-12-16 1992-10-05 Sony Corp

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