JPS5685929A - Switch circuit - Google Patents

Switch circuit

Info

Publication number
JPS5685929A
JPS5685929A JP16324979A JP16324979A JPS5685929A JP S5685929 A JPS5685929 A JP S5685929A JP 16324979 A JP16324979 A JP 16324979A JP 16324979 A JP16324979 A JP 16324979A JP S5685929 A JPS5685929 A JP S5685929A
Authority
JP
Japan
Prior art keywords
circuit
output
switch
clock
latching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16324979A
Other languages
Japanese (ja)
Other versions
JPH0113656B2 (en
Inventor
Mitsutoshi Yahagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP16324979A priority Critical patent/JPS5685929A/en
Publication of JPS5685929A publication Critical patent/JPS5685929A/en
Publication of JPH0113656B2 publication Critical patent/JPH0113656B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To prevent a malfunction error caused by chattering and static electricity, by supplying a switch operation detecting signal output from the FF, to the latching circuit, in the switch circuit which is composed of the latching circuit and the FF. CONSTITUTION:When the switch 4 is opened, an output of the NOR circuit 12 of the latching circuit 11 is ''1'', and the ''1'' signal is output from the output terminal Q of the FF5. In this case, the output of the NOR circuit 13 of the circuit 11 is held at ''0'' regardless of the clock phi1 and the output level of the circuit 12. Therefore, the circuit 13 is separated equivalently from the circuit 12, and the circuit 12 operates as an inverter. When a short-width pulse has been generated in the switch 4 by static electricity, etc., it becomes an inverted signal by the circuit 12, but it is not read to the FF5 unless it is generated at the same time as the clock phi2. When the switch 4 is closed, the circuit 12 is inverted to ''0'', and it is read to the FF5, synchronizing with the clock phi2. Even if chattering occurs at the time closing the switch 4, the output of the FF5 holds a state of ''0'' if it ends before rise of the clock phi2.
JP16324979A 1979-12-15 1979-12-15 Switch circuit Granted JPS5685929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16324979A JPS5685929A (en) 1979-12-15 1979-12-15 Switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16324979A JPS5685929A (en) 1979-12-15 1979-12-15 Switch circuit

Publications (2)

Publication Number Publication Date
JPS5685929A true JPS5685929A (en) 1981-07-13
JPH0113656B2 JPH0113656B2 (en) 1989-03-07

Family

ID=15770184

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16324979A Granted JPS5685929A (en) 1979-12-15 1979-12-15 Switch circuit

Country Status (1)

Country Link
JP (1) JPS5685929A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4883993A (en) * 1987-12-14 1989-11-28 Sgs-Thomson Microelectronics Srl. Antibounce circuit for digital circuits
US4926072A (en) * 1987-09-18 1990-05-15 Aisin Seiki Kabushikikaisha Noise elimination circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4926072A (en) * 1987-09-18 1990-05-15 Aisin Seiki Kabushikikaisha Noise elimination circuit
US4883993A (en) * 1987-12-14 1989-11-28 Sgs-Thomson Microelectronics Srl. Antibounce circuit for digital circuits

Also Published As

Publication number Publication date
JPH0113656B2 (en) 1989-03-07

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