JPS5679350A - Reducing conversion system of memory address space - Google Patents

Abstract

PURPOSE: To economically execute the reducing conversion of the memory address space and make unnecessary an extra memory space, by using a memory address space reduction converting circuit.

CONSTITUTION: The memory address space reduction converting circuit 2 consists of the address reduction converting memory ROM21, and the ROM21 is constituted, for instance, of 256 words × 7 bits. The high rank 3 bits among 9 bits of the Y part 11 of the memory logical register, and the high rank 5 bits among 9 bits of the X part 11, that is to say, 8 bits in all are input in the ROM21. And the partial pattern of 7 bits in all consisting of the high rank 3 bits of the Y part (9 bits) 31 of the memory physical register and the high rank 4 bits of the X part (9 bits) 32 is read out from the ROM21. The high rank 7 bits of the Y part 31, and the residual are made a column address of DRAM and a row address, respectively, by the correspondence of the physical address of the graphic memory obtained in this way, and the address of DRAM which is a graphic memory element. Thus, this system is economical since an extra memory space is not required.

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