JPS56760A - Control system for line speed - Google Patents

Control system for line speed

Info

Publication number
JPS56760A
JPS56760A JP7557979A JP7557979A JPS56760A JP S56760 A JPS56760 A JP S56760A JP 7557979 A JP7557979 A JP 7557979A JP 7557979 A JP7557979 A JP 7557979A JP S56760 A JPS56760 A JP S56760A
Authority
JP
Japan
Prior art keywords
pulse
line speed
register
fundamental
ofp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7557979A
Other languages
Japanese (ja)
Other versions
JPS5835425B2 (en
Inventor
Hikari Masujima
Akira Onodera
Mamoru Chino
Katsuo Uyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54075579A priority Critical patent/JPS5835425B2/en
Publication of JPS56760A publication Critical patent/JPS56760A/en
Publication of JPS5835425B2 publication Critical patent/JPS5835425B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To realize simple and effective line speed control system which can easily be applied to small sized station, by making variable the repetitive frequency of the fundamental clock by changing the initial value of register according to the line speed. CONSTITUTION:The output pulse of the clock oscillator 1 is started for the count from the content initially set to the register 2 at the advancement unit 3. When the content of the register 2 reaches a given value, the detector detects the overflow pulse OFP and inputs one clock pulse to the character assembling and disassembling circuit 6. Further, interruption is made to the processor by OFP and the register 2 is again initially set. By repeating the production of OFP and the initial set, the fundamental pulse of a given period can be fed to the circuit 6. By changing the initial set value of the processor 5 with the software control, the period of the fundamental pulse is variable and the circuit 6 determines the line speed handled with the period of the fundamental pulse. Accordingly, the number of circuits 6 can be determined by traffic intensity independently of the line speed, types and number, and this system can easily be applied to a small sized station.
JP54075579A 1979-06-18 1979-06-18 Line speed control method Expired JPS5835425B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54075579A JPS5835425B2 (en) 1979-06-18 1979-06-18 Line speed control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54075579A JPS5835425B2 (en) 1979-06-18 1979-06-18 Line speed control method

Publications (2)

Publication Number Publication Date
JPS56760A true JPS56760A (en) 1981-01-07
JPS5835425B2 JPS5835425B2 (en) 1983-08-02

Family

ID=13580234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54075579A Expired JPS5835425B2 (en) 1979-06-18 1979-06-18 Line speed control method

Country Status (1)

Country Link
JP (1) JPS5835425B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58140840A (en) * 1982-02-15 1983-08-20 Hitachi Ltd Baud rate controller
US6453758B1 (en) 1999-06-11 2002-09-24 Msp Corporation Efficient high-productivity cascade impactors
US6595368B2 (en) 2000-12-08 2003-07-22 Msp Corporation Pre-separator for inlets of cascade impactors
US10527189B2 (en) 2015-11-13 2020-01-07 Ihi Corporation Valve actuator for an electrically actuated poppet valve including a continuously variable transmission and a power free latching mechanism

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH054607Y2 (en) * 1985-07-04 1993-02-04

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58140840A (en) * 1982-02-15 1983-08-20 Hitachi Ltd Baud rate controller
US6453758B1 (en) 1999-06-11 2002-09-24 Msp Corporation Efficient high-productivity cascade impactors
US6723568B1 (en) 1999-06-11 2004-04-20 Msp Corporation Method and apparatus for cascade impactor testing of inhalable drug therapies recovery for chemical analysis
US6595368B2 (en) 2000-12-08 2003-07-22 Msp Corporation Pre-separator for inlets of cascade impactors
US10527189B2 (en) 2015-11-13 2020-01-07 Ihi Corporation Valve actuator for an electrically actuated poppet valve including a continuously variable transmission and a power free latching mechanism

Also Published As

Publication number Publication date
JPS5835425B2 (en) 1983-08-02

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