JPS5674726A - Automatic return control system at the time of fault - Google Patents

Automatic return control system at the time of fault

Info

Publication number
JPS5674726A
JPS5674726A JP15059179A JP15059179A JPS5674726A JP S5674726 A JPS5674726 A JP S5674726A JP 15059179 A JP15059179 A JP 15059179A JP 15059179 A JP15059179 A JP 15059179A JP S5674726 A JPS5674726 A JP S5674726A
Authority
JP
Japan
Prior art keywords
unit
time
hss
signal line
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15059179A
Other languages
Japanese (ja)
Inventor
Toshio Mazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15059179A priority Critical patent/JPS5674726A/en
Publication of JPS5674726A publication Critical patent/JPS5674726A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To make it possible to automatically return to the original state at the time of fault, by providing the superviosory means for deciding the time of falut on the electronic device which continuously executes the data transmission by repeating the hand shaking sequence HSS.
CONSTITUTION: For instance, it is assumed that as the first stage of HSS, the address information through the address and data bus 5 from the central operation processing unit 1, and the read or write instruction from the request signal line 7 have been sent out to the memory control device MCU3 at the same time. In response to said processing, MCU3 sends back an acknolwdge signal ACK to the unit 1, completes HSS, and after that, transfers a data by the bus 5. The ACk signal line 8 is also connected to the control circuit 9, the circuit 9 supervises an input signal, sends a reset signal to the unit 1 through the reset signal line 10 in case when the generation time intervals are longer than specified, and resets the unit 1 to its initial status. Accordingly, the data transmission device is never brought to a quiescent state from which it cannot get out.
COPYRIGHT: (C)1981,JPO&Japio
JP15059179A 1979-11-22 1979-11-22 Automatic return control system at the time of fault Pending JPS5674726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15059179A JPS5674726A (en) 1979-11-22 1979-11-22 Automatic return control system at the time of fault

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15059179A JPS5674726A (en) 1979-11-22 1979-11-22 Automatic return control system at the time of fault

Publications (1)

Publication Number Publication Date
JPS5674726A true JPS5674726A (en) 1981-06-20

Family

ID=15500225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15059179A Pending JPS5674726A (en) 1979-11-22 1979-11-22 Automatic return control system at the time of fault

Country Status (1)

Country Link
JP (1) JPS5674726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080334A (en) * 1983-10-07 1985-05-08 Olympus Optical Co Ltd Reset circuit of endoscope image pickup system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080334A (en) * 1983-10-07 1985-05-08 Olympus Optical Co Ltd Reset circuit of endoscope image pickup system

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