JPS5672725A - Bus control system - Google Patents

Bus control system

Info

Publication number
JPS5672725A
JPS5672725A JP15029879A JP15029879A JPS5672725A JP S5672725 A JPS5672725 A JP S5672725A JP 15029879 A JP15029879 A JP 15029879A JP 15029879 A JP15029879 A JP 15029879A JP S5672725 A JPS5672725 A JP S5672725A
Authority
JP
Japan
Prior art keywords
bus
permission
state mode
signals
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15029879A
Other languages
Japanese (ja)
Inventor
Toshio Karino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15029879A priority Critical patent/JPS5672725A/en
Publication of JPS5672725A publication Critical patent/JPS5672725A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To make it possible to realize a bus control circuit of high reliability by giving the permission to use a bus after making sure that the bus line is in three- state mode securely.
CONSTITUTION: Requests to use a bus, when arriving from bus request signal lines 1-1...1-n, are latched in latch circuits 3-1...3-n as far as the three-state mode of bus line 2 is detected by three-state detecting circuit 9 and permission signals are outputted to bus-use permission signals 5-1...5-n. The bus permission signals and bus request signals are AND-ed by ANDs 6-1...6-n, and according to their outputs, one of data from data signal lines 8-1...8-n is sent out to bus line 2. As the bus using device finishes the use of the bus, bus 2 is placed in three-state mode. Thus, the high-reliability bus control circuit can be realized by giving the permission to use the next bus after making sure that the bus line is in three-state mode securely.
COPYRIGHT: (C)1981,JPO&Japio
JP15029879A 1979-11-20 1979-11-20 Bus control system Pending JPS5672725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15029879A JPS5672725A (en) 1979-11-20 1979-11-20 Bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15029879A JPS5672725A (en) 1979-11-20 1979-11-20 Bus control system

Publications (1)

Publication Number Publication Date
JPS5672725A true JPS5672725A (en) 1981-06-17

Family

ID=15493938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15029879A Pending JPS5672725A (en) 1979-11-20 1979-11-20 Bus control system

Country Status (1)

Country Link
JP (1) JPS5672725A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814228A (en) * 1981-07-18 1983-01-27 Nippon Telegr & Teleph Corp <Ntt> Information processor
JPS58115514A (en) * 1981-12-29 1983-07-09 Hitachi Ltd Connection detecting system
JPH07281918A (en) * 1994-04-13 1995-10-27 Nec Corp Switching circuit for duplex signal relay system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814228A (en) * 1981-07-18 1983-01-27 Nippon Telegr & Teleph Corp <Ntt> Information processor
JPS58115514A (en) * 1981-12-29 1983-07-09 Hitachi Ltd Connection detecting system
JPH07281918A (en) * 1994-04-13 1995-10-27 Nec Corp Switching circuit for duplex signal relay system

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