JPS5667424A - Control method of duplex bus - Google Patents

Control method of duplex bus

Info

Publication number
JPS5667424A
JPS5667424A JP14206179A JP14206179A JPS5667424A JP S5667424 A JPS5667424 A JP S5667424A JP 14206179 A JP14206179 A JP 14206179A JP 14206179 A JP14206179 A JP 14206179A JP S5667424 A JPS5667424 A JP S5667424A
Authority
JP
Japan
Prior art keywords
error
bus
cut
control method
permanent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14206179A
Other languages
Japanese (ja)
Inventor
Yoshihiro Miyazaki
Ryoichi Takamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14206179A priority Critical patent/JPS5667424A/en
Publication of JPS5667424A publication Critical patent/JPS5667424A/en
Pending legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To prevent the separation of a system due to momentary error and to cut off the system quickly at a permanent error, by deciding as a permanent error in the single system bus, only when twice or more errors are generated within a given time and by stopping the use of the bus.
CONSTITUTION: A timer 23 starts the operation when an error detection signal 26 is on, and when the 2nd error detection signal 26 is detected within the timer set time, a timer set FF24 is set. This is decided as a permanent error in a single system bus and the use of the bus is stopped. Thus, the cut-off of the system by a momentary error is prevented and the system is quickly cut off at the permanent error.
COPYRIGHT: (C)1981,JPO&Japio
JP14206179A 1979-11-05 1979-11-05 Control method of duplex bus Pending JPS5667424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14206179A JPS5667424A (en) 1979-11-05 1979-11-05 Control method of duplex bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14206179A JPS5667424A (en) 1979-11-05 1979-11-05 Control method of duplex bus

Publications (1)

Publication Number Publication Date
JPS5667424A true JPS5667424A (en) 1981-06-06

Family

ID=15306505

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14206179A Pending JPS5667424A (en) 1979-11-05 1979-11-05 Control method of duplex bus

Country Status (1)

Country Link
JP (1) JPS5667424A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137054A (en) * 1981-10-01 1983-08-15 ストレイタス・コンピユ−タ・インコ−ポレイテツド Highly reliable digital data processor
JPH06332813A (en) * 1993-05-25 1994-12-02 Nec Corp Fault detection system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137054A (en) * 1981-10-01 1983-08-15 ストレイタス・コンピユ−タ・インコ−ポレイテツド Highly reliable digital data processor
JPH0531173B2 (en) * 1981-10-01 1993-05-11 Sutoreitasu Konpyuuta Inc
JPH06332813A (en) * 1993-05-25 1994-12-02 Nec Corp Fault detection system

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