JPS5660022A - Processing method and device for semiconductor wafer - Google Patents

Processing method and device for semiconductor wafer

Info

Publication number
JPS5660022A
JPS5660022A JP13616479A JP13616479A JPS5660022A JP S5660022 A JPS5660022 A JP S5660022A JP 13616479 A JP13616479 A JP 13616479A JP 13616479 A JP13616479 A JP 13616479A JP S5660022 A JPS5660022 A JP S5660022A
Authority
JP
Japan
Prior art keywords
wafer
reverse side
abrasive solution
semiconductor wafer
soaked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13616479A
Other languages
Japanese (ja)
Inventor
Fumio Shimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13616479A priority Critical patent/JPS5660022A/en
Publication of JPS5660022A publication Critical patent/JPS5660022A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

PURPOSE:To increase the gettering effect and the productivity of the subject semiconductor wafer by a method wherein the reverse side of the wafer is soaked in an abrasive solution and a uniform damaged layer is formed on the reverse side of the wafer while ultrasonic vibrations are being applied. CONSTITUTION:The wafer 2 is sticked to a wafer supporting disk 1 with the reverse side facing outside, it is soaked into an abrasive solution 5 filled in an abrasive solution vessel 4, vibrations are given by an ultrasonic vibration generator 3 and a damaged layer is formed with an excellent reproducibility on the reverse side of the wafer. As a uniform back-distortion processed layer ie formed hereby, a large quantity of wafers can be manufactured simultaneously.
JP13616479A 1979-10-22 1979-10-22 Processing method and device for semiconductor wafer Pending JPS5660022A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13616479A JPS5660022A (en) 1979-10-22 1979-10-22 Processing method and device for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13616479A JPS5660022A (en) 1979-10-22 1979-10-22 Processing method and device for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS5660022A true JPS5660022A (en) 1981-05-23

Family

ID=15168811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13616479A Pending JPS5660022A (en) 1979-10-22 1979-10-22 Processing method and device for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS5660022A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01143223A (en) * 1987-11-28 1989-06-05 Toshiba Corp Surface treatment of semiconductor substrate
JPH01143224A (en) * 1987-11-28 1989-06-05 Toshiba Corp Surface treatment of semiconductor substrate
US5071776A (en) * 1987-11-28 1991-12-10 Kabushiki Kaisha Toshiba Wafer processsing method for manufacturing wafers having contaminant-gettering damage on one surface
JP2006303223A (en) * 2005-04-21 2006-11-02 Disco Abrasive Syst Ltd Processing method of wafer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01143223A (en) * 1987-11-28 1989-06-05 Toshiba Corp Surface treatment of semiconductor substrate
JPH01143224A (en) * 1987-11-28 1989-06-05 Toshiba Corp Surface treatment of semiconductor substrate
US4971920A (en) * 1987-11-28 1990-11-20 Kabushiki Kaisha Toshiba Gettering method for semiconductor wafers
US4980300A (en) * 1987-11-28 1990-12-25 Kabushiki Kaisha Toshiba Gettering method for a semiconductor wafer
US5071776A (en) * 1987-11-28 1991-12-10 Kabushiki Kaisha Toshiba Wafer processsing method for manufacturing wafers having contaminant-gettering damage on one surface
JPH0524661B2 (en) * 1987-11-28 1993-04-08 Toshiba Kk
JP2006303223A (en) * 2005-04-21 2006-11-02 Disco Abrasive Syst Ltd Processing method of wafer

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