JPS5659333A - Peripheral equipment control system - Google Patents

Peripheral equipment control system

Info

Publication number
JPS5659333A
JPS5659333A JP13352379A JP13352379A JPS5659333A JP S5659333 A JPS5659333 A JP S5659333A JP 13352379 A JP13352379 A JP 13352379A JP 13352379 A JP13352379 A JP 13352379A JP S5659333 A JPS5659333 A JP S5659333A
Authority
JP
Japan
Prior art keywords
output
abnormal
test input
input
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13352379A
Other languages
Japanese (ja)
Inventor
Yuji Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13352379A priority Critical patent/JPS5659333A/en
Publication of JPS5659333A publication Critical patent/JPS5659333A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enhance the reliability by doubly providing the controllers equipped with both the test input/output function and the peripheral interruption function, between CPU and the peripheral equipments.
CONSTITUTION: At the time of the process input/output by CPU, in case when abnormal has been detected, the test input/output are executed by use of the test input/output functions 7a, 7b of the controllers 4a, 4b from CPU5, and if the test input/output are normal, it is decided that the controllers 4a, 4b are normal and the process input/output units 1W3 are abnormal. On the other hand, if the test input/output are abnormal, it is decided that the process input/output units 1W3 are normal, and the controller 4a or 4b is abnormal, and thereafter, CPU executes the processing by the other controller without using the abnormal controller.
COPYRIGHT: (C)1981,JPO&Japio
JP13352379A 1979-10-18 1979-10-18 Peripheral equipment control system Pending JPS5659333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13352379A JPS5659333A (en) 1979-10-18 1979-10-18 Peripheral equipment control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13352379A JPS5659333A (en) 1979-10-18 1979-10-18 Peripheral equipment control system

Publications (1)

Publication Number Publication Date
JPS5659333A true JPS5659333A (en) 1981-05-22

Family

ID=15106773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13352379A Pending JPS5659333A (en) 1979-10-18 1979-10-18 Peripheral equipment control system

Country Status (1)

Country Link
JP (1) JPS5659333A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219050A (en) * 1986-03-19 1987-09-26 Nec Corp Configuration modifying system for duplicated terminal controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62219050A (en) * 1986-03-19 1987-09-26 Nec Corp Configuration modifying system for duplicated terminal controller

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