JPS5657327A - Chattering eliminating circuit - Google Patents

Chattering eliminating circuit

Info

Publication number
JPS5657327A
JPS5657327A JP13393879A JP13393879A JPS5657327A JP S5657327 A JPS5657327 A JP S5657327A JP 13393879 A JP13393879 A JP 13393879A JP 13393879 A JP13393879 A JP 13393879A JP S5657327 A JPS5657327 A JP S5657327A
Authority
JP
Japan
Prior art keywords
circuit
change
output
input level
fixed period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13393879A
Other languages
Japanese (ja)
Other versions
JPS6226602B2 (en
Inventor
Hiroshi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seikosha KK
Original Assignee
Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seikosha KK filed Critical Seikosha KK
Priority to JP13393879A priority Critical patent/JPS5657327A/en
Publication of JPS5657327A publication Critical patent/JPS5657327A/en
Publication of JPS6226602B2 publication Critical patent/JPS6226602B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Keying Circuit Devices (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To prevent the malfunction which occurs in case the chattering lasts long, by giving no change to the output state of a memory circuit although the input level may fluctuate within a fixed period of the pulse and then producing the output corresponding to the input level through the memory circuit in case the input has no change. CONSTITUTION:The pulses in a fixed period and supplied to the terminal P1 are supplied to the reset terminals of the detecting circuits F1 and F2 comprising the FF which detects the change of the input level within a fixed period. And the input signal supplied through the terminal P2 is applied to the set terminal. The output of one side in the circuits F1 and F2 each is applied to the memory circuit F3 consisting of the FF via the 1st control circuit S1; while the output of the other side is applied to the 2nd control circuit S2 via the gate circuit G. And furthermore, the pulse having a certain cycle is applied to the clock terminal of the circuit F3. And when the fact that no change is given to the input level within a fixed period is detected by the circuits F1 and F2, the output corresponding to the input level is stored in the circuit F3 for output and through the circuit S1. And in case a change is detected, the output of the circuit F3 is held at the level before the change by the circuit S2. Thus the malfunction can be avoided.
JP13393879A 1979-10-16 1979-10-16 Chattering eliminating circuit Granted JPS5657327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13393879A JPS5657327A (en) 1979-10-16 1979-10-16 Chattering eliminating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13393879A JPS5657327A (en) 1979-10-16 1979-10-16 Chattering eliminating circuit

Publications (2)

Publication Number Publication Date
JPS5657327A true JPS5657327A (en) 1981-05-19
JPS6226602B2 JPS6226602B2 (en) 1987-06-10

Family

ID=15116572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13393879A Granted JPS5657327A (en) 1979-10-16 1979-10-16 Chattering eliminating circuit

Country Status (1)

Country Link
JP (1) JPS5657327A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0119401A2 (en) * 1983-02-18 1984-09-26 Heidelberger Druckmaschinen Aktiengesellschaft Circuit arrangement for light barriers, e.g. for sheet control means in a printing machine
JP2015002405A (en) * 2013-06-14 2015-01-05 スパンション エルエルシー Noise detection circuit and reception circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50123248U (en) * 1974-03-22 1975-10-08
JPS50146254A (en) * 1974-05-14 1975-11-22
JPS5246749A (en) * 1975-10-11 1977-04-13 Nippon Syst Kogyo Kk Noise eliminator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50123248U (en) * 1974-03-22 1975-10-08
JPS50146254A (en) * 1974-05-14 1975-11-22
JPS5246749A (en) * 1975-10-11 1977-04-13 Nippon Syst Kogyo Kk Noise eliminator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0119401A2 (en) * 1983-02-18 1984-09-26 Heidelberger Druckmaschinen Aktiengesellschaft Circuit arrangement for light barriers, e.g. for sheet control means in a printing machine
JP2015002405A (en) * 2013-06-14 2015-01-05 スパンション エルエルシー Noise detection circuit and reception circuit

Also Published As

Publication number Publication date
JPS6226602B2 (en) 1987-06-10

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