JPS5657137A - Trigger signal generating system - Google Patents

Trigger signal generating system

Info

Publication number
JPS5657137A
JPS5657137A JP13215979A JP13215979A JPS5657137A JP S5657137 A JPS5657137 A JP S5657137A JP 13215979 A JP13215979 A JP 13215979A JP 13215979 A JP13215979 A JP 13215979A JP S5657137 A JPS5657137 A JP S5657137A
Authority
JP
Japan
Prior art keywords
signal
circuit
gate
trigger
trigger signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13215979A
Other languages
Japanese (ja)
Inventor
Tadashi Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13215979A priority Critical patent/JPS5657137A/en
Publication of JPS5657137A publication Critical patent/JPS5657137A/en
Pending legal-status Critical Current

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  • Emergency Protection Circuit Devices (AREA)

Abstract

PURPOSE: To prevent the trouble where storage contents do not agree with the trigger signal, by generating the trigger signal by the agreement signal between the select signal of a condition set switch and the sampling signal.
CONSTITUTION: Input signals I1WIn are subjected to waveform shaping by line receiver D and are sent to sampling circuit S and are sampled. The output of circuit S is sent to memory M and is written at the same period as clock 5. The output of circuit S is sent to the trigger circuit also. The trigger circuit consists of AND gate A3, NOR gate A2, and NAND gate A4, and further, trigger signal TG generated first after the end of reset signal 6 is stored by flip-flop F. Further, the AND circuit constitution for the high, off, or low select signal and the sampling signal is given by AND gate A1, and clock 5 is supplied through gate A so that the trigger signal can be generated even if the off signal is selected. As a result, the trouble where storage contents do not agree with the trigger signal can be prevented.
COPYRIGHT: (C)1981,JPO&Japio
JP13215979A 1979-10-13 1979-10-13 Trigger signal generating system Pending JPS5657137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13215979A JPS5657137A (en) 1979-10-13 1979-10-13 Trigger signal generating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13215979A JPS5657137A (en) 1979-10-13 1979-10-13 Trigger signal generating system

Publications (1)

Publication Number Publication Date
JPS5657137A true JPS5657137A (en) 1981-05-19

Family

ID=15074735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13215979A Pending JPS5657137A (en) 1979-10-13 1979-10-13 Trigger signal generating system

Country Status (1)

Country Link
JP (1) JPS5657137A (en)

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