JPS56500870A - - Google Patents

Info

Publication number
JPS56500870A
JPS56500870A JP50186480A JP50186480A JPS56500870A JP S56500870 A JPS56500870 A JP S56500870A JP 50186480 A JP50186480 A JP 50186480A JP 50186480 A JP50186480 A JP 50186480A JP S56500870 A JPS56500870 A JP S56500870A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50186480A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS56500870A publication Critical patent/JPS56500870A/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233Integrated injection logic structures [I2L]
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/288Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Shift Register Type Memory (AREA)
JP50186480A 1979-07-19 1980-07-07 Pending JPS56500870A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US5900879A 1979-07-19 1979-07-19

Publications (1)

Publication Number Publication Date
JPS56500870A true JPS56500870A (en) 1981-06-25

Family

ID=22020240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50186480A Pending JPS56500870A (en) 1979-07-19 1980-07-07

Country Status (4)

Country Link
EP (1) EP0032154A4 (en)
JP (1) JPS56500870A (en)
BR (1) BR8008718A (en)
WO (1) WO1981000332A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3302248A1 (en) * 1983-01-24 1984-07-26 Siemens AG, 1000 Berlin und 8000 München SLIDING REGISTER

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3655999A (en) * 1971-04-05 1972-04-11 Ibm Shift register
GB1494481A (en) * 1973-12-21 1977-12-07 Mullard Ltd Electrical circuits comprising master/slave bistable arrangements
DE2442773C3 (en) * 1974-09-06 1978-12-14 Deutsche Itt Industries Gmbh, 7800 Freiburg Integrated master-slave flip-flop circuit
GB1543716A (en) * 1975-03-11 1979-04-04 Plessey Co Ltd Injection logic arrangements
US4197470A (en) * 1976-07-15 1980-04-08 Texas Instruments Incorporated Triggerable flip-flop
US4150392A (en) * 1976-07-31 1979-04-17 Nippon Gakki Seizo Kabushiki Kaisha Semiconductor integrated flip-flop circuit device including merged bipolar and field effect transistors
US4099263A (en) * 1976-11-04 1978-07-04 Motorola Inc. Buffering for an I2 L memory cell
US4156154A (en) * 1976-12-14 1979-05-22 Tokyo Shibaura Electric Co., Ltd. Flip-flop circuit
US4160173A (en) * 1976-12-14 1979-07-03 Tokyo Shibaura Electric Co., Ltd. Logic circuit with two pairs of cross-coupled nand/nor gates
JPS5847092B2 (en) * 1976-12-14 1983-10-20 株式会社東芝 logic circuit

Also Published As

Publication number Publication date
WO1981000332A1 (en) 1981-02-05
BR8008718A (en) 1981-06-09
EP0032154A1 (en) 1981-07-22
EP0032154A4 (en) 1981-11-24

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