JPS5643562A - Frequency counter - Google Patents

Frequency counter

Info

Publication number
JPS5643562A
JPS5643562A JP11948779A JP11948779A JPS5643562A JP S5643562 A JPS5643562 A JP S5643562A JP 11948779 A JP11948779 A JP 11948779A JP 11948779 A JP11948779 A JP 11948779A JP S5643562 A JPS5643562 A JP S5643562A
Authority
JP
Japan
Prior art keywords
circuit
counter
frequency division
input
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11948779A
Other languages
Japanese (ja)
Inventor
Hideji Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11948779A priority Critical patent/JPS5643562A/en
Publication of JPS5643562A publication Critical patent/JPS5643562A/en
Pending legal-status Critical Current

Links

Landscapes

  • Measuring Frequencies, Analyzing Spectra (AREA)

Abstract

PURPOSE: To consitute the counter circuit by a simple decimal counter, by providing a frequency division circuit whose regular gate time is set to 2-n seconds and frequency division ratio is 10l.2-n, on the input circuit of the counter decimally counting an input signal which is taken in by the regular gate time.
CONSTITUTION: An input signal provided to the terminal 1 is added to the input of the frequency division circuit 2, a signal of its output is input to the decimal counter 4 through the gate circuit 3, and it is decimally counted. Also, the contents of each frequency divider of the counter 4 are provided to the latch circuit 5, and are displayed in the indicator 9 through the decoder 8. A quartz for a clock is used for the timing generator 6 which provides a timing signal to the gate circuit 3, the counter 4 and the latch circuit 5, and the gate time provided to the gate circuit 3 is set to 2-nsec. Also, the frequency division ratio of the frequency division circuit 2 is set to 10l.2-n. Thus, a quartz vibrator for a clock, which is high in precision and low in cost, can be used for the timing generator 6 as it is, and also the circuit can be formed by binary frequency division. Therefore, the counter circuit can be formed by a simple decimal counter.
COPYRIGHT: (C)1981,JPO&Japio
JP11948779A 1979-09-18 1979-09-18 Frequency counter Pending JPS5643562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11948779A JPS5643562A (en) 1979-09-18 1979-09-18 Frequency counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11948779A JPS5643562A (en) 1979-09-18 1979-09-18 Frequency counter

Publications (1)

Publication Number Publication Date
JPS5643562A true JPS5643562A (en) 1981-04-22

Family

ID=14762480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11948779A Pending JPS5643562A (en) 1979-09-18 1979-09-18 Frequency counter

Country Status (1)

Country Link
JP (1) JPS5643562A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6118514U (en) * 1984-07-06 1986-02-03 日立電線株式会社 woven cable

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6118514U (en) * 1984-07-06 1986-02-03 日立電線株式会社 woven cable

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