JPS5636752A - Digital processor - Google Patents

Digital processor

Info

Publication number
JPS5636752A
JPS5636752A JP11223279A JP11223279A JPS5636752A JP S5636752 A JPS5636752 A JP S5636752A JP 11223279 A JP11223279 A JP 11223279A JP 11223279 A JP11223279 A JP 11223279A JP S5636752 A JPS5636752 A JP S5636752A
Authority
JP
Japan
Prior art keywords
digital processing
processing circuit
rectangular
circuit
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11223279A
Other languages
Japanese (ja)
Inventor
Yukio Hosokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Storage Battery Co Ltd
Original Assignee
Japan Storage Battery Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Storage Battery Co Ltd filed Critical Japan Storage Battery Co Ltd
Priority to JP11223279A priority Critical patent/JPS5636752A/en
Publication of JPS5636752A publication Critical patent/JPS5636752A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To attain a self-diagnosis by providing the 1st rectangular-wave signal generating circuit, a digital processing circuit having a program to generate the 2nd rectangular-wave signal and logic circuits that detect levels of both the rectangular waves.
CONSTITUTION: Oscillating circuit 3 outputs the 1st rectangular wave (a) to digital processing circuit 2 and logic circuits 4 and 6. Digital processing circuit 2 generates an output (2nd rectangular wave) for a fault diagnosis which becomes high in level only when input waveform (a) is at a high level. This 2nd rectangular waves are also applied to logic circuits 4 and 6. While waveform (a) stays at the high level, the 1st logic circuit 4 judges that when a fault diagnosis output from digital processing circuit 2 never becomes high in level even once, digital processing circuit 2 is out of order. The 2nd logic circuit 6, when waveform (a) is at the low level and the fault diagnosis output is at the high level, judges that digital processing circuit 2 is in trouble.
COPYRIGHT: (C)1981,JPO&Japio
JP11223279A 1979-08-31 1979-08-31 Digital processor Pending JPS5636752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11223279A JPS5636752A (en) 1979-08-31 1979-08-31 Digital processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11223279A JPS5636752A (en) 1979-08-31 1979-08-31 Digital processor

Publications (1)

Publication Number Publication Date
JPS5636752A true JPS5636752A (en) 1981-04-10

Family

ID=14581542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11223279A Pending JPS5636752A (en) 1979-08-31 1979-08-31 Digital processor

Country Status (1)

Country Link
JP (1) JPS5636752A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09171471A (en) * 1995-12-21 1997-06-30 Kofu Nippon Denki Kk Inter-lsi asynchronous data transfer circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09171471A (en) * 1995-12-21 1997-06-30 Kofu Nippon Denki Kk Inter-lsi asynchronous data transfer circuit

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