JPS5635469A - Manufacture of complementary semiconductor device - Google Patents

Manufacture of complementary semiconductor device

Info

Publication number
JPS5635469A
JPS5635469A JP11146579A JP11146579A JPS5635469A JP S5635469 A JPS5635469 A JP S5635469A JP 11146579 A JP11146579 A JP 11146579A JP 11146579 A JP11146579 A JP 11146579A JP S5635469 A JPS5635469 A JP S5635469A
Authority
JP
Japan
Prior art keywords
well
forming
semiconductor device
si3n4
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11146579A
Other languages
Japanese (ja)
Inventor
Shigero Kuninobu
Eisuke Ichinohe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11146579A priority Critical patent/JPS5635469A/en
Publication of JPS5635469A publication Critical patent/JPS5635469A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To easily and exactly obtain the well of the complementary semiconductor device by forming a pattern for forming a field region, then forming the well thereon, and thereafter forming a field insulating film thereon. CONSTITUTION:An Si3N4 23 is selectively formed on an SiO2 22 on an N type Si substrate 21. A resist mask 25 is used to implant P type ion thereon, and the well 26 is formed thereon. The resist mask 25 is then removed, is driven in, and the well 26' is thus formed. With the film 23 as a mask a field oxide film 27 is formed thereon, the Si3N4 23 and the SiO2 22 are then removed, and a gate oxide film 28 is formed thereon. Thereafter the complementary SOS devices are respectively formed on the substrate 21 and the well 26'. According to this configuration, pattern information for forming the well can be secured in the respective steps without increasing the steps, there is no step of exposing the Si surface, and the characteristics cannot be deteriorated, and the device can be accurately and easily manufactured.
JP11146579A 1979-08-30 1979-08-30 Manufacture of complementary semiconductor device Pending JPS5635469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11146579A JPS5635469A (en) 1979-08-30 1979-08-30 Manufacture of complementary semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11146579A JPS5635469A (en) 1979-08-30 1979-08-30 Manufacture of complementary semiconductor device

Publications (1)

Publication Number Publication Date
JPS5635469A true JPS5635469A (en) 1981-04-08

Family

ID=14561923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11146579A Pending JPS5635469A (en) 1979-08-30 1979-08-30 Manufacture of complementary semiconductor device

Country Status (1)

Country Link
JP (1) JPS5635469A (en)

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