JPS5635413A - Method of etching semiconductor crystal layer at gas phase - Google Patents

Method of etching semiconductor crystal layer at gas phase

Info

Publication number
JPS5635413A
JPS5635413A JP11057379A JP11057379A JPS5635413A JP S5635413 A JPS5635413 A JP S5635413A JP 11057379 A JP11057379 A JP 11057379A JP 11057379 A JP11057379 A JP 11057379A JP S5635413 A JPS5635413 A JP S5635413A
Authority
JP
Japan
Prior art keywords
substrate
gas phase
point
source metal
upstream
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11057379A
Other languages
Japanese (ja)
Inventor
Kenichi Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11057379A priority Critical patent/JPS5635413A/en
Publication of JPS5635413A publication Critical patent/JPS5635413A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H01L21/02661—In-situ cleaning

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To make etching uniform, by placing a source metal element at an upstream point in a reaction tube of quartz and a crystal substrate at a downstream point in the tube and setting the temperature of the heated substrate low at its upstream portion and high at its downstream portion when etching the surface of the substrate at gas phase before growing operation. CONSTITUTION:A source metal Ga, from which a grown film is made, is placed at an upstream point in a reaction tube of quartz around which an electric furnace 12 is installed. A plurality of crystal substrates 17 set on a substrate carrier 18 are placed at a downstream point in the reaction tube. The interior of the tube is heated at a prescribed temperature to educe the source metal Ga on the substrates 17. Before the eduction work, the surface of each substrate 17 is etched at gas phase in such a manner that mixed gas of AsCl or HCl with H2 is introduced through an inlet pipe 14 inserted to the vicinity of the substrate 17 and mixed gas of AsCl with H2 is introduced through another inlet pipe 15 located not near the substrate and the temperature of the upstream portion of the substrate is set slightly higher than that of its downstream portion.
JP11057379A 1979-08-29 1979-08-29 Method of etching semiconductor crystal layer at gas phase Pending JPS5635413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11057379A JPS5635413A (en) 1979-08-29 1979-08-29 Method of etching semiconductor crystal layer at gas phase

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11057379A JPS5635413A (en) 1979-08-29 1979-08-29 Method of etching semiconductor crystal layer at gas phase

Publications (1)

Publication Number Publication Date
JPS5635413A true JPS5635413A (en) 1981-04-08

Family

ID=14539253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11057379A Pending JPS5635413A (en) 1979-08-29 1979-08-29 Method of etching semiconductor crystal layer at gas phase

Country Status (1)

Country Link
JP (1) JPS5635413A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63271935A (en) * 1987-04-28 1988-11-09 Matsushita Electric Ind Co Ltd Plasma processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63271935A (en) * 1987-04-28 1988-11-09 Matsushita Electric Ind Co Ltd Plasma processor

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