JPS5627551A - Digital arithmetic modulator and demodulator - Google Patents

Digital arithmetic modulator and demodulator

Info

Publication number
JPS5627551A
JPS5627551A JP10262279A JP10262279A JPS5627551A JP S5627551 A JPS5627551 A JP S5627551A JP 10262279 A JP10262279 A JP 10262279A JP 10262279 A JP10262279 A JP 10262279A JP S5627551 A JPS5627551 A JP S5627551A
Authority
JP
Japan
Prior art keywords
circuit
carrier
amplitude
modulating
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10262279A
Other languages
Japanese (ja)
Inventor
Yutaka Suzuki
Yoshihiro Jinbo
Shuji Yoshino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10262279A priority Critical patent/JPS5627551A/en
Publication of JPS5627551A publication Critical patent/JPS5627551A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36—Modulator circuits; Transmitter circuits
    • H04L27/361—Modulation using a single or unspecified number of carriers, e.g. with separate stages of phase and amplitude modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits
    • H04L27/3818—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers
    • H04L27/3836—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers in which the carrier is recovered using the received modulated signal or the received IF signal, e.g. by detecting a pilot or by frequency multiplication

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To reduce the arithmetic quantity that a modulating-demodulating circuit requires, by obtaining a clock direct from a carrier. CONSTITUTION:Phase modulating circuit 106, supplied with sampled values (+ or -1) of the 1st carrier amplitude from clock generator 102, provides phase modulation and amplitude modulating circuit 107, receiving the output of speed converter 104 and that of phase modulating circuit 106, performs multiplication. Since the output of phase modulating circuit 10 has values + or -1 and + or -1/2, its multiplication is realized by a polarity inverting circuit and one-bit shift circuit. A signal input from transmission line 114 is A/D-converted and then supplied to shift register 118 by way of amplitude equalizer 117 to generate a clock synchronizing with a reception carrier frequency and meanwhile, detecting circuit 123 multiplies it by its reproduced carrier for detection.
JP10262279A 1979-08-10 1979-08-10 Digital arithmetic modulator and demodulator Pending JPS5627551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10262279A JPS5627551A (en) 1979-08-10 1979-08-10 Digital arithmetic modulator and demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10262279A JPS5627551A (en) 1979-08-10 1979-08-10 Digital arithmetic modulator and demodulator

Publications (1)

Publication Number Publication Date
JPS5627551A true JPS5627551A (en) 1981-03-17

Family

ID=14332337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10262279A Pending JPS5627551A (en) 1979-08-10 1979-08-10 Digital arithmetic modulator and demodulator

Country Status (1)

Country Link
JP (1) JPS5627551A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59207768A (en) * 1983-04-22 1984-11-24 ジ−メンス・アクチエンゲゼルシヤフト Digital type dc/ac amplitude modulating method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59207768A (en) * 1983-04-22 1984-11-24 ジ−メンス・アクチエンゲゼルシヤフト Digital type dc/ac amplitude modulating method
JPH0137057B2 (en) * 1983-04-22 1989-08-03 Siemens Ag

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