JPS5625295A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5625295A
JPS5625295A JP10057279A JP10057279A JPS5625295A JP S5625295 A JPS5625295 A JP S5625295A JP 10057279 A JP10057279 A JP 10057279A JP 10057279 A JP10057279 A JP 10057279A JP S5625295 A JPS5625295 A JP S5625295A
Authority
JP
Japan
Prior art keywords
address
logic level
held
decoder
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10057279A
Other languages
Japanese (ja)
Inventor
Koichi Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10057279A priority Critical patent/JPS5625295A/en
Publication of JPS5625295A publication Critical patent/JPS5625295A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To make it possible to write information to all address at a time by providing a simultaneous selecting-setting method so that when an external signal is supplied, all address lines are selected. CONSTITUTION:Holding external terminal 10 at a high logic level turns on MOSFET switch 11 and the terminal is grounded. As a result, address latch signals input to X-address decoder 21 becomes uncomplementary and are all held at a low logic level. Consequently, outputs of decoder 21 are all held at the high logic level and gates of all elements in P-ROM cell 20 with the X address can be applied with the high voltage. Similarly, holding external control terminal 12 at the high level results in that outputs of Y decoder 18 are all held at the high logic level. As a result, sources in cell 20 with the Y address can be applied with the high voltage. Consequently, all addresses can be written at a time. Therefore, the write time of the P-ROM element for a test can greatly be shortened.
JP10057279A 1979-08-06 1979-08-06 Semiconductor device Pending JPS5625295A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10057279A JPS5625295A (en) 1979-08-06 1979-08-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10057279A JPS5625295A (en) 1979-08-06 1979-08-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5625295A true JPS5625295A (en) 1981-03-11

Family

ID=14277610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10057279A Pending JPS5625295A (en) 1979-08-06 1979-08-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5625295A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0089364A1 (en) * 1981-09-28 1983-09-28 Motorola, Inc. Eeprom with bulk zero program capability
EP0090005A1 (en) * 1981-09-28 1983-10-05 Motorola, Inc. Column and row erasable eeprom
EP0120485A2 (en) * 1983-03-24 1984-10-03 Kabushiki Kaisha Toshiba Memory system
EP0149043A2 (en) * 1983-12-30 1985-07-24 International Business Machines Corporation Random access memory
EP0202910A2 (en) * 1985-05-20 1986-11-26 Fujitsu Limited Decoder circuit for a semiconductor memory device
EP0223188A2 (en) * 1985-11-20 1987-05-27 Fujitsu Limited Semiconductor programmable memory device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178939A (en) * 1974-12-30 1976-07-09 Fujitsu Ltd
JPS52130536A (en) * 1976-04-26 1977-11-01 Toshiba Corp Semiconductor memory unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178939A (en) * 1974-12-30 1976-07-09 Fujitsu Ltd
JPS52130536A (en) * 1976-04-26 1977-11-01 Toshiba Corp Semiconductor memory unit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0089364A1 (en) * 1981-09-28 1983-09-28 Motorola, Inc. Eeprom with bulk zero program capability
EP0090005A1 (en) * 1981-09-28 1983-10-05 Motorola, Inc. Column and row erasable eeprom
EP0120485A2 (en) * 1983-03-24 1984-10-03 Kabushiki Kaisha Toshiba Memory system
EP0149043A2 (en) * 1983-12-30 1985-07-24 International Business Machines Corporation Random access memory
EP0149043B1 (en) * 1983-12-30 1991-08-28 International Business Machines Corporation Random access memory
EP0202910A2 (en) * 1985-05-20 1986-11-26 Fujitsu Limited Decoder circuit for a semiconductor memory device
EP0223188A2 (en) * 1985-11-20 1987-05-27 Fujitsu Limited Semiconductor programmable memory device

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