JPS562031A - Input circuit - Google Patents

Input circuit

Info

Publication number
JPS562031A
JPS562031A JP7647979A JP7647979A JPS562031A JP S562031 A JPS562031 A JP S562031A JP 7647979 A JP7647979 A JP 7647979A JP 7647979 A JP7647979 A JP 7647979A JP S562031 A JPS562031 A JP S562031A
Authority
JP
Japan
Prior art keywords
signal
circuits
terminals
decimal
output terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7647979A
Other languages
Japanese (ja)
Inventor
Fukuyoshi Watanabe
Shigeki Kumagai
Eiji Masuda
Yukihiro Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7647979A priority Critical patent/JPS562031A/en
Publication of JPS562031A publication Critical patent/JPS562031A/en
Pending legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To simplify inspection in manufacture and input setting in use by providing the method of coding a binary signal into a decimal signal and outputting a signal from one of its output terminals, and another method of outputting a signal from an output terminal corresponding to an input terminal.
CONSTITUTION: Integrated circuit 31 for digital timepieces consists of internal circuits 321W327 whose internal states are set by external signals, the 1st interface IF33 with binary signal input terminals I1WI3 and decimal-coded signal output terminals O1WO7, the 2nd IF34 with signal input terminals IaWId and signal output terminals OaWOd corresponding to them, and OR circuits 351W354 which receive signals from output terminals O3, O5WO7, and OaWOd. Output terminals O1, O2 and O4 of IF33 and the outputs of circuits 351W354 are connected to input terminals O1, O2, O4, O3, and O5'WO7' of circuits 32. To input terminals 361W367 of circuit 31, switch SW371W377 are connected; and for function inspection in manufacture, SW371W373 are driven by a three-bit binary signal to output decimal signals 0W7 and in use, SW371W377 are driven to set decimal signals 0W7.
COPYRIGHT: (C)1981,JPO&Japio
JP7647979A 1979-06-18 1979-06-18 Input circuit Pending JPS562031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7647979A JPS562031A (en) 1979-06-18 1979-06-18 Input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7647979A JPS562031A (en) 1979-06-18 1979-06-18 Input circuit

Publications (1)

Publication Number Publication Date
JPS562031A true JPS562031A (en) 1981-01-10

Family

ID=13606322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7647979A Pending JPS562031A (en) 1979-06-18 1979-06-18 Input circuit

Country Status (1)

Country Link
JP (1) JPS562031A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027512U (en) * 1983-08-01 1985-02-25 日本圧電気株式会社 amplifier power supply

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027512U (en) * 1983-08-01 1985-02-25 日本圧電気株式会社 amplifier power supply

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