JPS56169474A - Picture noise removal device - Google Patents

Picture noise removal device

Info

Publication number
JPS56169474A
JPS56169474A JP7460080A JP7460080A JPS56169474A JP S56169474 A JPS56169474 A JP S56169474A JP 7460080 A JP7460080 A JP 7460080A JP 7460080 A JP7460080 A JP 7460080A JP S56169474 A JPS56169474 A JP S56169474A
Authority
JP
Japan
Prior art keywords
input
gate
delay lines
removal device
noise removal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7460080A
Other languages
Japanese (ja)
Inventor
Satoshi Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP7460080A priority Critical patent/JPS56169474A/en
Publication of JPS56169474A publication Critical patent/JPS56169474A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Picture Signal Circuits (AREA)
  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To enable the noise rejecting processing in real time, by making the noise rejecting processing through the hardware constitution in 6 sets of horizontal delay lines and two vertical delay lines and a logical circuit. CONSTITUTION:The 1st-6-th horizontal delay lines 5, 6, 8, 9, 11, 12 and the 1st and 2nd vertical delay lines 7, 10 constitute a 3X3 picture element matrix. Further, a signal outputted at the same time from an output terminal A of a binary video signal V, output terminals B, C, E, F, H, I of the 1st-6th horizontal delay lines, scans 9 video elements (not shown) at the same time. A logical circuit L consists of an 8-input AND gate 13, 8-input NOR gate 14, 2-input OR gate 15, inverter 16, 2-input OR gate 17, inverter 18, 2-input AND gates 19, 20, and 2-input OR gate 21.
JP7460080A 1980-05-31 1980-05-31 Picture noise removal device Pending JPS56169474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7460080A JPS56169474A (en) 1980-05-31 1980-05-31 Picture noise removal device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7460080A JPS56169474A (en) 1980-05-31 1980-05-31 Picture noise removal device

Publications (1)

Publication Number Publication Date
JPS56169474A true JPS56169474A (en) 1981-12-26

Family

ID=13551805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7460080A Pending JPS56169474A (en) 1980-05-31 1980-05-31 Picture noise removal device

Country Status (1)

Country Link
JP (1) JPS56169474A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6609488B2 (en) * 2000-10-13 2003-08-26 Kabushiki Kaisha Tokai Rika Denki Seisakusho Apparatus and procedure for starting vehicle engine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6609488B2 (en) * 2000-10-13 2003-08-26 Kabushiki Kaisha Tokai Rika Denki Seisakusho Apparatus and procedure for starting vehicle engine

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