JPS5616244A - Microprogram loading system - Google Patents
Microprogram loading systemInfo
- Publication number
- JPS5616244A JPS5616244A JP9194379A JP9194379A JPS5616244A JP S5616244 A JPS5616244 A JP S5616244A JP 9194379 A JP9194379 A JP 9194379A JP 9194379 A JP9194379 A JP 9194379A JP S5616244 A JPS5616244 A JP S5616244A
- Authority
- JP
- Japan
- Prior art keywords
- address
- instruction
- register
- load
- execution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To enable interruption with priority partially for the load instruction during the execution of other micro instructions, by providing the shunt register shunting the execution address and the load address storage means storing the load address in the address control circuit.
CONSTITUTION: The instruction in the control memory 3 is indicated with the address control circuit 2, the instruction is sequentially read out in the instruction register 4, and the instruction is decoded at the decoder 5 to execute the instruction. During the execution of this instruction, when the address control part 21 of the circuit 2 receives the request to load the data designated from the data transfer control circuit 1 in the control memory 3, the control memory address executed next in the control memory address register 24 is shunted at the shunt address register 22. Further, the address for the load instruction execution of the load address register 23 stored in the control memory is transferred to the register 24, this instruction word is executed via the register 4 and the decoder 5, and the data is loaded to the control memory 3 from the external memory 6.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9194379A JPS5616244A (en) | 1979-07-19 | 1979-07-19 | Microprogram loading system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9194379A JPS5616244A (en) | 1979-07-19 | 1979-07-19 | Microprogram loading system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5616244A true JPS5616244A (en) | 1981-02-17 |
Family
ID=14040669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9194379A Pending JPS5616244A (en) | 1979-07-19 | 1979-07-19 | Microprogram loading system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5616244A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS48103143A (en) * | 1972-03-08 | 1973-12-25 | ||
JPS51113432A (en) * | 1975-03-28 | 1976-10-06 | Hitachi Ltd | Input output control system |
JPS5248444A (en) * | 1975-10-15 | 1977-04-18 | Nec Corp | Microprogram interruption reopening system |
JPS5365029A (en) * | 1976-11-24 | 1978-06-10 | Hitachi Ltd | Microprogram control system |
-
1979
- 1979-07-19 JP JP9194379A patent/JPS5616244A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS48103143A (en) * | 1972-03-08 | 1973-12-25 | ||
JPS51113432A (en) * | 1975-03-28 | 1976-10-06 | Hitachi Ltd | Input output control system |
JPS5248444A (en) * | 1975-10-15 | 1977-04-18 | Nec Corp | Microprogram interruption reopening system |
JPS5365029A (en) * | 1976-11-24 | 1978-06-10 | Hitachi Ltd | Microprogram control system |
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