JPS56147220A - Clock controller - Google Patents

Clock controller

Info

Publication number
JPS56147220A
JPS56147220A JP5085580A JP5085580A JPS56147220A JP S56147220 A JPS56147220 A JP S56147220A JP 5085580 A JP5085580 A JP 5085580A JP 5085580 A JP5085580 A JP 5085580A JP S56147220 A JPS56147220 A JP S56147220A
Authority
JP
Japan
Prior art keywords
circuit
sck12
sck
power consumption
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5085580A
Other languages
Japanese (ja)
Other versions
JPS6148726B2 (en
Inventor
Junichi Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5085580A priority Critical patent/JPS56147220A/en
Publication of JPS56147220A publication Critical patent/JPS56147220A/en
Publication of JPS6148726B2 publication Critical patent/JPS6148726B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

PURPOSE:To reduce power consumption of the integrated circuit, by stopping the system clock (SCK) and the basic clock (CK) when the data processing is not executed and by shortening the time of the transition state of the C-MOS constitution. CONSTITUTION:During the data processing, CK oscillating circuit 1 oscillates to supply basic CK11 to SCK generating circuit 2. Circuit 2 frequency-divides CK11 to supply SCK12 to data processing device 5. Device 5 executes various data processings synchronously with SCK12. During this time, power consumption based on the transition state of the C-MOS constitution in device 5 is increased in proportion to the frequency of SCK12. When device has nothing to execute, hold signal 15 is sent to CK control circuit 3. Circuit 3 receives signal 15 and sends oscillation stop signal 13 and SCK supply signal 14 to circuits 1 and 2 respectively to stop supplying of CK11 and SCK12. The operation state of the circuit is not changed, and device 5 becomes stable, and C-MOS has only a leak current, thus power consumption is reduced.
JP5085580A 1980-04-17 1980-04-17 Clock controller Granted JPS56147220A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5085580A JPS56147220A (en) 1980-04-17 1980-04-17 Clock controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5085580A JPS56147220A (en) 1980-04-17 1980-04-17 Clock controller

Publications (2)

Publication Number Publication Date
JPS56147220A true JPS56147220A (en) 1981-11-16
JPS6148726B2 JPS6148726B2 (en) 1986-10-25

Family

ID=12870331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5085580A Granted JPS56147220A (en) 1980-04-17 1980-04-17 Clock controller

Country Status (1)

Country Link
JP (1) JPS56147220A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58101233U (en) * 1981-12-25 1983-07-09 富士通株式会社 Standby mode control device
JPS6118021A (en) * 1984-07-04 1986-01-25 Hitachi Ltd Data processor
JPS61155930U (en) * 1985-03-20 1986-09-27
JPS61164532U (en) * 1985-04-02 1986-10-13
EP0656579A2 (en) * 1993-12-01 1995-06-07 Advanced Micro Devices, Inc. Power management for computer system
US5548765A (en) * 1990-08-28 1996-08-20 Seiko Epson Corporation Power saving display subsystem for portable computers

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4876922U (en) * 1971-12-25 1973-09-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4876922U (en) * 1971-12-25 1973-09-22

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58101233U (en) * 1981-12-25 1983-07-09 富士通株式会社 Standby mode control device
JPH035948Y2 (en) * 1981-12-25 1991-02-15
JPS6118021A (en) * 1984-07-04 1986-01-25 Hitachi Ltd Data processor
JPS61155930U (en) * 1985-03-20 1986-09-27
JPH0431620Y2 (en) * 1985-03-20 1992-07-29
JPS61164532U (en) * 1985-04-02 1986-10-13
JPH0431621Y2 (en) * 1985-04-02 1992-07-29
US5548765A (en) * 1990-08-28 1996-08-20 Seiko Epson Corporation Power saving display subsystem for portable computers
EP0656579A2 (en) * 1993-12-01 1995-06-07 Advanced Micro Devices, Inc. Power management for computer system
EP0656579A3 (en) * 1993-12-01 1995-08-02 Advanced Micro Devices Inc Power management for computer system.
US5628020A (en) * 1993-12-01 1997-05-06 Advanced Micro Devices System oscillator gating technique for power management within a computer system

Also Published As

Publication number Publication date
JPS6148726B2 (en) 1986-10-25

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