JPS56145415A - Direct memory access device - Google Patents

Direct memory access device

Info

Publication number
JPS56145415A
JPS56145415A JP4722880A JP4722880A JPS56145415A JP S56145415 A JPS56145415 A JP S56145415A JP 4722880 A JP4722880 A JP 4722880A JP 4722880 A JP4722880 A JP 4722880A JP S56145415 A JPS56145415 A JP S56145415A
Authority
JP
Japan
Prior art keywords
memory access
direct memory
memory
bus
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4722880A
Other languages
Japanese (ja)
Inventor
Takayuki Torii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP4722880A priority Critical patent/JPS56145415A/en
Publication of JPS56145415A publication Critical patent/JPS56145415A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To improve the performance of a direct memory access transfer device, by interchanging information between CPU and a direct memory access controller in the cycle of direct memory access. CONSTITUTION:To bus 2 connected to and controlled by CPU1, main memory 3 is connected. To bus 5 connected to and controlled by direct memory access DMA controller 4, external auxiliary memory 6 and local memory 7 which transfers data during the DMA cycle of memory 6 are also connected. Then, buses 2 and 5 are connected together via duplex buffer gate 8, which is composed of tristate type TTL element 9 whose output impedance can be brought under high/low switching control. During the DMA cycle, gate 8 is switched to the high impedance. Consequently, CPU1 never stops even in the DMA cycle and continues data processing with memory 3 via bus 2.
JP4722880A 1980-04-10 1980-04-10 Direct memory access device Pending JPS56145415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4722880A JPS56145415A (en) 1980-04-10 1980-04-10 Direct memory access device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4722880A JPS56145415A (en) 1980-04-10 1980-04-10 Direct memory access device

Publications (1)

Publication Number Publication Date
JPS56145415A true JPS56145415A (en) 1981-11-12

Family

ID=12769340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4722880A Pending JPS56145415A (en) 1980-04-10 1980-04-10 Direct memory access device

Country Status (1)

Country Link
JP (1) JPS56145415A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59157740A (en) * 1983-02-25 1984-09-07 Nec Home Electronics Ltd Data transfer method of microcomputer system
JPH01300361A (en) * 1988-05-28 1989-12-04 Nec Eng Ltd Microprocessor system
US4991217A (en) * 1984-11-30 1991-02-05 Ibm Corporation Dual processor speech recognition system with dedicated data acquisition bus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59157740A (en) * 1983-02-25 1984-09-07 Nec Home Electronics Ltd Data transfer method of microcomputer system
US4991217A (en) * 1984-11-30 1991-02-05 Ibm Corporation Dual processor speech recognition system with dedicated data acquisition bus
JPH01300361A (en) * 1988-05-28 1989-12-04 Nec Eng Ltd Microprocessor system

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