JPS5612859A - Boosting circuit - Google Patents

Abstract

PURPOSE:To obtain exactly quaternary level voltage with less current consumption in a boosting circuit by switching a switching element by three type timing signals in every cycle in combination of a switching element and a capacitor. CONSTITUTION:The drain electrode of a MOS transistor Trl is connected through a capacitor C1 and the source and the drain of a transistor Tr2 in series to the (-) electrode of a DC power supply E, and a timing signal A1 is applied to the gate electrode of the transistor Tr2. A timing signal A2 is connected through an inverter 14 to the gate electrode of a transistor Tr5, the output of the transistor Tr5 is further connected through an inverter 15 to the gate of a transistor Tr4 and through an inverter 16 to the gate electrode of a transistor Tr6. On the other hand, a timing signal A3 is supplied through inverters 17, 18 to the gates of transistors Tr7, Tr9, and through an inverter 19 to the gate electrode of a transistor Tr8. In this manner it can reduce the current consumption so as to exactly obtain a quaternary level voltage.