JPS56126351A - Quality deciding circuit of pulse pattern - Google Patents

Quality deciding circuit of pulse pattern

Info

Publication number
JPS56126351A
JPS56126351A JP3068580A JP3068580A JPS56126351A JP S56126351 A JPS56126351 A JP S56126351A JP 3068580 A JP3068580 A JP 3068580A JP 3068580 A JP3068580 A JP 3068580A JP S56126351 A JPS56126351 A JP S56126351A
Authority
JP
Japan
Prior art keywords
pulse
terminal
shift
bit
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3068580A
Other languages
Japanese (ja)
Inventor
Yusaku Kamibayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3068580A priority Critical patent/JPS56126351A/en
Publication of JPS56126351A publication Critical patent/JPS56126351A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PURPOSE:To avoid an effect to the scale of a circuit that is caused by an increment/ decrement of the bit number, by using the error pulse of the n-bit serial pattern as the shift pulse in a PCM communication device. CONSTITUTION:The n-bit serial pulse pattern is introduced to the error detecting circuit 22 via the terminal 21, and the shift pulse 23 is delivered only for the bit in which the error pulse exists to be turned into the shift pulse to the 2-stage shift register 24. The set pulse of the register 24 is applied to the point immediately before the time point of the 1st bit of the n-bit serial pulse pattern via the terminal 25 to set all contents of the register at ''1''. On the other hand, the shift data ''0'' is applied via the terminal 26. As a result, ''1'' is delivered through the decision output terminal 27 when the pulse train containing no error pulse at all is applied to the terminal 21. And an error pulse >=2 bits, if exists, emerges ''0'' at the shift data of the terminal 26 as the decision output.
JP3068580A 1980-03-11 1980-03-11 Quality deciding circuit of pulse pattern Pending JPS56126351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3068580A JPS56126351A (en) 1980-03-11 1980-03-11 Quality deciding circuit of pulse pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3068580A JPS56126351A (en) 1980-03-11 1980-03-11 Quality deciding circuit of pulse pattern

Publications (1)

Publication Number Publication Date
JPS56126351A true JPS56126351A (en) 1981-10-03

Family

ID=12310537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3068580A Pending JPS56126351A (en) 1980-03-11 1980-03-11 Quality deciding circuit of pulse pattern

Country Status (1)

Country Link
JP (1) JPS56126351A (en)

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