JPS56125857A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS56125857A JPS56125857A JP2877080A JP2877080A JPS56125857A JP S56125857 A JPS56125857 A JP S56125857A JP 2877080 A JP2877080 A JP 2877080A JP 2877080 A JP2877080 A JP 2877080A JP S56125857 A JPS56125857 A JP S56125857A
- Authority
- JP
- Japan
- Prior art keywords
- wirings
- layer
- aluminum
- silicon nitride
- organosiloxane resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
PURPOSE:To obtain a multilayer wiring structure in which an insulation of the lower wirings is kept well between each other and a flat degree of a surface formed with the upper wirings by a method wherein a concave between the lower wirings is filled with an organosiloxane resin and covered with inorganic insulating layer. CONSTITUTION:An insulating film 2 such as silicon dioxide is formed on the surface of a semiconductor substrate 1 formed with an element and perforated a window. Then, the lower aluminum wirings 3 are formed. Then, the organosiloxane resin layer 4 is formed and applied a plasma-etching to expose the aluminum wirings 3. Subsequently, a silicon nitride layer 5 is formed by a chemical gaseous phase growing method, and wiring connection window 7 is formed in the silicon nitride layer 5 by using a photoresist mask 6. Thereafter, the photoresist 6 is removed, an aluminum layer being attached and applied a patterning to form the upper wirings 8.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2877080A JPS56125857A (en) | 1980-03-07 | 1980-03-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2877080A JPS56125857A (en) | 1980-03-07 | 1980-03-07 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56125857A true JPS56125857A (en) | 1981-10-02 |
JPS6227745B2 JPS6227745B2 (en) | 1987-06-16 |
Family
ID=12257636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2877080A Granted JPS56125857A (en) | 1980-03-07 | 1980-03-07 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56125857A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0147203A2 (en) * | 1983-12-27 | 1985-07-03 | Kabushiki Kaisha Toshiba | Method of forming multilayer interconnections for a semiconductor device |
JPS6325929A (en) * | 1986-07-17 | 1988-02-03 | Nec Corp | Semiconductor integrated circuit |
-
1980
- 1980-03-07 JP JP2877080A patent/JPS56125857A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0147203A2 (en) * | 1983-12-27 | 1985-07-03 | Kabushiki Kaisha Toshiba | Method of forming multilayer interconnections for a semiconductor device |
JPS6325929A (en) * | 1986-07-17 | 1988-02-03 | Nec Corp | Semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6227745B2 (en) | 1987-06-16 |
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