JPS56125846A - Surface treatment of semiconductor - Google Patents

Surface treatment of semiconductor

Info

Publication number
JPS56125846A
JPS56125846A JP2790380A JP2790380A JPS56125846A JP S56125846 A JPS56125846 A JP S56125846A JP 2790380 A JP2790380 A JP 2790380A JP 2790380 A JP2790380 A JP 2790380A JP S56125846 A JPS56125846 A JP S56125846A
Authority
JP
Japan
Prior art keywords
film
interface
semiconductor
substrate
implanted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2790380A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP2790380A priority Critical patent/JPS56125846A/en
Publication of JPS56125846A publication Critical patent/JPS56125846A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To form a semiconductor device in stable and excellent characteristic by decreasing an interface level density existing in the interface by a method wherein C ion is implanted in the interface of the semiconductor substrate and an insulating film formed on the semiconductor substrate surface. CONSTITUTION:An SiO2 film and an Si3N4 film are selectively formed on the P type Si substrate 1 and heat-treated in an oxidation atmosphere to form a field oxidation film 4, and then, the surface covered with the oxidation film is slightly oxidized to form a thin (e.g. 500-1,000Angstrom ) SiO2 film and then further, the C ion is implanted in the interface of the substrate 1 and the SiO2 films 4, 5 and anealed after the formation of an implanted region 6. Whereby the interface level density on the semiconductor surface to be formed with a gate-electrode thereon and a channel just below the gate insulating film 5 is made approximately zero to enable the semiconductor device of MOSIC etc. excellent in the characteristic to be obtained.
JP2790380A 1980-03-07 1980-03-07 Surface treatment of semiconductor Pending JPS56125846A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2790380A JPS56125846A (en) 1980-03-07 1980-03-07 Surface treatment of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2790380A JPS56125846A (en) 1980-03-07 1980-03-07 Surface treatment of semiconductor

Publications (1)

Publication Number Publication Date
JPS56125846A true JPS56125846A (en) 1981-10-02

Family

ID=12233838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2790380A Pending JPS56125846A (en) 1980-03-07 1980-03-07 Surface treatment of semiconductor

Country Status (1)

Country Link
JP (1) JPS56125846A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4992840A (en) * 1989-09-21 1991-02-12 Hewlett-Packard Company Carbon doping MOSFET substrate to suppress hit electron trapping
US5051377A (en) * 1988-09-01 1991-09-24 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
US5139869A (en) * 1988-09-01 1992-08-18 Wolfgang Euen Thin dielectric layer on a substrate
US5268311A (en) * 1988-09-01 1993-12-07 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051377A (en) * 1988-09-01 1991-09-24 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
US5139869A (en) * 1988-09-01 1992-08-18 Wolfgang Euen Thin dielectric layer on a substrate
US5268311A (en) * 1988-09-01 1993-12-07 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
US4992840A (en) * 1989-09-21 1991-02-12 Hewlett-Packard Company Carbon doping MOSFET substrate to suppress hit electron trapping

Similar Documents

Publication Publication Date Title
JPS56125847A (en) Surface treatment of semiconductor
JPS56125846A (en) Surface treatment of semiconductor
JPS5736842A (en) Semiconductor integrated circuit device
JPS54146584A (en) Manufacture of semiconductor device
JPS56124270A (en) Manufacture of semiconductor device
JPS5795625A (en) Manufacture of semiconductor device
JPS5688358A (en) Manufacture of semiconductor device
JPS56125848A (en) Surface treatment of semiconductor
JPS56103445A (en) Production of semiconductor device
JPS56111243A (en) Preparation of semiconductor device
JPS56147466A (en) Semiconductor device
JPS5766671A (en) Semiconductor device
JPS57113250A (en) Semiconductor device
JPS56111241A (en) Preparation of semiconductor device
JPS5753981A (en) Manufacture of semiconductor device
JPS54109385A (en) Field effect semiconductor device of high dielectric strength
JPS5323574A (en) Forming method of silicon oxide film
JPS5739579A (en) Mos semiconductor device and manufacture thereof
JPS5497380A (en) Manufacture of semiconductor device
JPS56111265A (en) Manufacture of semiconductor device
JPS5572080A (en) Production of silicone gate type semiconductor device
JPS577121A (en) Manufacture of semiconductor device
JPS5596680A (en) Method of fabricating mos semiconductor device
JPS56111240A (en) Semiconductor device and manufacture thereof
JPS572576A (en) Semiconductor device