JPS56124247A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56124247A
JPS56124247A JP2430681A JP2430681A JPS56124247A JP S56124247 A JPS56124247 A JP S56124247A JP 2430681 A JP2430681 A JP 2430681A JP 2430681 A JP2430681 A JP 2430681A JP S56124247 A JPS56124247 A JP S56124247A
Authority
JP
Japan
Prior art keywords
electrodes
joining
section
sections
membrane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2430681A
Other languages
Japanese (ja)
Other versions
JPS594853B2 (en
Inventor
Shinkichi Okutsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56024306A priority Critical patent/JPS594853B2/en
Publication of JPS56124247A publication Critical patent/JPS56124247A/en
Publication of JPS594853B2 publication Critical patent/JPS594853B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05073Single internal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • H01L2224/05558Shape in side view conformal layer on a patterned surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4807Shape of bonding interfaces, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4845Details of ball bonds
    • H01L2224/48451Shape
    • H01L2224/48453Shape of the interface with the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent an electrode section from corrosion, by providing second conductor layer to be embedded in an opening section of a protective membrane of polyimide resin, etc., and fixing a joining wire to this layer. CONSTITUTION:When first step electrodes 12 and 13 are provided, their joining sections 14 and 15 are made much smaller than the conventional. A polyimide resin membrane 16 is laminated on the electrodes 12 and 13 and also on an insulating membrane 21, suspension capacity is reduced by adjusting the thickness, an opening is provided on the joining sections 14 and 15, second step electrodes 17 and 18 are provided, and an arrangement is made so that the joint center of joining lines 19 and 20 comes to the opening section. In this mechanism, when the second step electrodes 17 and 18 are corroded, while the corrosion continuously develops at sections C and D, it stops halfway and does not go as far as section A. And therefore, a wire does not break even at the time when an Al electrode is small, and besides, as the second electrodes 17 and 18 are able to be formed in a longer size, operation becomes facilitated.
JP56024306A 1981-02-23 1981-02-23 semiconductor equipment Expired JPS594853B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56024306A JPS594853B2 (en) 1981-02-23 1981-02-23 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56024306A JPS594853B2 (en) 1981-02-23 1981-02-23 semiconductor equipment

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP48027070A Division JPS5748854B2 (en) 1973-03-09 1973-03-09

Publications (2)

Publication Number Publication Date
JPS56124247A true JPS56124247A (en) 1981-09-29
JPS594853B2 JPS594853B2 (en) 1984-02-01

Family

ID=12134483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56024306A Expired JPS594853B2 (en) 1981-02-23 1981-02-23 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS594853B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2604029A1 (en) * 1986-09-16 1988-03-18 Toshiba Kk INTEGRATED CIRCUIT CHIP HAVING IMPROVED OUTPUT TERMINALS

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110462816B (en) 2017-03-31 2023-09-19 琳得科株式会社 Method for manufacturing semiconductor device and adhesive sheet
JP6764524B2 (en) 2017-03-31 2020-09-30 リンテック株式会社 Adhesive sheet
CN110461978B (en) 2017-03-31 2022-04-19 琳得科株式会社 Adhesive sheet
KR102454056B1 (en) 2017-03-31 2022-10-14 린텍 가부시키가이샤 Semiconductor device manufacturing method and double-sided adhesive sheet
JP6764526B2 (en) 2017-03-31 2020-09-30 リンテック株式会社 Adhesive sheet
KR102526158B1 (en) 2017-08-09 2023-04-26 린텍 가부시키가이샤 Heating and peeling method of processing inspection object
JP7129110B2 (en) 2018-10-02 2022-09-01 リンテック株式会社 Laminate and method for producing cured sealing body
WO2021200789A1 (en) 2020-03-31 2021-10-07 リンテック株式会社 Double-sided adhesive sheet, and method for manufacturing semiconductor device
KR20230069910A (en) 2020-09-14 2023-05-19 린텍 가부시키가이샤 Manufacturing method of adhesive sheet and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4870475A (en) * 1971-12-23 1973-09-25
JPS49116961A (en) * 1973-03-09 1974-11-08

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4870475A (en) * 1971-12-23 1973-09-25
JPS49116961A (en) * 1973-03-09 1974-11-08

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2604029A1 (en) * 1986-09-16 1988-03-18 Toshiba Kk INTEGRATED CIRCUIT CHIP HAVING IMPROVED OUTPUT TERMINALS

Also Published As

Publication number Publication date
JPS594853B2 (en) 1984-02-01

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