JPS56122240A - Frequency setting device of frequency synthesizer - Google Patents
Frequency setting device of frequency synthesizerInfo
- Publication number
- JPS56122240A JPS56122240A JP2490680A JP2490680A JPS56122240A JP S56122240 A JPS56122240 A JP S56122240A JP 2490680 A JP2490680 A JP 2490680A JP 2490680 A JP2490680 A JP 2490680A JP S56122240 A JPS56122240 A JP S56122240A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- counter
- control
- discontinuous
- synthesizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 abstract 2
- 230000007423 decrease Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To ensure a consecutive control of frequency for a frequency synthesizer having a number of digital phase synchronous loops, by installing a digital hysteresis circuit between the phase synchronous loop and the counter of the frequency control part. CONSTITUTION:A double-loop synthesizer is formed with the PLL6 and 7, the reference frequency oscillator 8, the multistage up-counter 9 and the pulse generator 10 each. Then a digital hysteresis circuit 12 is provided between the counter 9 of the frequency control circuit 11 and the frequency set signal line connecting the PLL6 and 7. As a result, a control is secured to avoid a coincidence for the discontinuous point of the frequency change of the voltage control oscillator (VCO) 61 and 62 each when the count data of the counter 9 increases in the up-direction and decreases in the down-direction respectively. Thus the discontinuous point is set in such range that gives no disturbance to the operation of the width of frequency hysteresis. As a result, a smooth reception is ensured just with a discontinuous action caused although the frequency is searched at the area near the bondary where a discontinuous state is caused.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55024906A JPS6014532B2 (en) | 1980-02-29 | 1980-02-29 | Frequency synthesizer frequency setting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55024906A JPS6014532B2 (en) | 1980-02-29 | 1980-02-29 | Frequency synthesizer frequency setting device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56122240A true JPS56122240A (en) | 1981-09-25 |
JPS6014532B2 JPS6014532B2 (en) | 1985-04-13 |
Family
ID=12151215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55024906A Expired JPS6014532B2 (en) | 1980-02-29 | 1980-02-29 | Frequency synthesizer frequency setting device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6014532B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59127428A (en) * | 1983-01-12 | 1984-07-23 | Marantz Japan Inc | Pll circuit for prevention against disturbance due to spurious generation |
EP0378231A2 (en) * | 1989-01-13 | 1990-07-18 | Sony Corporation | Frequency synthesizer |
KR100498411B1 (en) * | 1997-10-24 | 2005-12-08 | 삼성전자주식회사 | Method for controlling frequency lock and pll therefor |
-
1980
- 1980-02-29 JP JP55024906A patent/JPS6014532B2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59127428A (en) * | 1983-01-12 | 1984-07-23 | Marantz Japan Inc | Pll circuit for prevention against disturbance due to spurious generation |
EP0378231A2 (en) * | 1989-01-13 | 1990-07-18 | Sony Corporation | Frequency synthesizer |
KR100498411B1 (en) * | 1997-10-24 | 2005-12-08 | 삼성전자주식회사 | Method for controlling frequency lock and pll therefor |
Also Published As
Publication number | Publication date |
---|---|
JPS6014532B2 (en) | 1985-04-13 |
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