JPS56121123A - Monitor control system - Google Patents
Monitor control systemInfo
- Publication number
- JPS56121123A JPS56121123A JP2317680A JP2317680A JPS56121123A JP S56121123 A JPS56121123 A JP S56121123A JP 2317680 A JP2317680 A JP 2317680A JP 2317680 A JP2317680 A JP 2317680A JP S56121123 A JPS56121123 A JP S56121123A
- Authority
- JP
- Japan
- Prior art keywords
- central processing
- excellency
- processing part
- input
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To improve the processing performance of a central processing part by interrupting the central processing part when an excellency signal shows defection during a read of return data. CONSTITUTION:Information is sent to device 13 to be controlled via input-output interface part 12 by the output instruction of central processing part 11. On the basis of this information, device 13 to be controlled operates and sends an excellency signal regarding its operation result and return information to input-output part 12. Then, central processing part 11 counts the time until the excellency signal from device 13 to be controlled is sent back to input-output part 12 after the output instruction. When the excellency signal is not returned from device 13 to be controlled in a certain time, input-output part 12 discriminates defection and interrupts central processing part 11 via interruption line 21. Thus, an input instruction for the confirmation of the excellency signal from central processing part 11 can be omitted, so that the processing performance of central processing part 11 is improved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2317680A JPS56121123A (en) | 1980-02-26 | 1980-02-26 | Monitor control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2317680A JPS56121123A (en) | 1980-02-26 | 1980-02-26 | Monitor control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56121123A true JPS56121123A (en) | 1981-09-22 |
Family
ID=12103317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2317680A Pending JPS56121123A (en) | 1980-02-26 | 1980-02-26 | Monitor control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56121123A (en) |
-
1980
- 1980-02-26 JP JP2317680A patent/JPS56121123A/en active Pending
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