JPS56119986A - Charge pumping memory - Google Patents

Charge pumping memory

Info

Publication number
JPS56119986A
JPS56119986A JP2434080A JP2434080A JPS56119986A JP S56119986 A JPS56119986 A JP S56119986A JP 2434080 A JP2434080 A JP 2434080A JP 2434080 A JP2434080 A JP 2434080A JP S56119986 A JPS56119986 A JP S56119986A
Authority
JP
Japan
Prior art keywords
region
bit line
separation
channel
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2434080A
Other languages
Japanese (ja)
Other versions
JPS6410946B2 (en
Inventor
Nobuo Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2434080A priority Critical patent/JPS56119986A/en
Publication of JPS56119986A publication Critical patent/JPS56119986A/en
Publication of JPS6410946B2 publication Critical patent/JPS6410946B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

PURPOSE:To decrease area per cell and make possible higher integration by performing all of the separation between memory cells using a bit line commonly by p-n junctions. CONSTITUTION:A deep (n') type region 20 for separation is formed at the center of a shallow n<+> type region 12 connected to a power source line VCC and a deep n<+> region 28 for separation reaching the surface of a substrate 2 is also provided right under the central part of the region 10 connected to a bit line BL. The region 28 is formed by same ion implantation process as that for the region 20. A source- drain region 10 connected to the bit line of adjacent cells Q2, Q3 is used commonly, and the contact hole 26 of the region 10 and the bit line BL is one, thus the cell area is decreased. When in operation the bit line BL is set at 0V and the word line WL2 at positive potential, a channel inversion layer is formed only on the surface of the p type region 4a of the cell Q2 and when gate voltage is turned off, the channel disappears and the charge in that channel is injected into the region 4a.
JP2434080A 1980-02-28 1980-02-28 Charge pumping memory Granted JPS56119986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2434080A JPS56119986A (en) 1980-02-28 1980-02-28 Charge pumping memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2434080A JPS56119986A (en) 1980-02-28 1980-02-28 Charge pumping memory

Publications (2)

Publication Number Publication Date
JPS56119986A true JPS56119986A (en) 1981-09-19
JPS6410946B2 JPS6410946B2 (en) 1989-02-22

Family

ID=12135443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2434080A Granted JPS56119986A (en) 1980-02-28 1980-02-28 Charge pumping memory

Country Status (1)

Country Link
JP (1) JPS56119986A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0136819A2 (en) * 1983-09-05 1985-04-10 Hitachi, Ltd. Semiconductor memory
EP1180799A2 (en) 2000-08-17 2002-02-20 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0136819A2 (en) * 1983-09-05 1985-04-10 Hitachi, Ltd. Semiconductor memory
EP1180799A2 (en) 2000-08-17 2002-02-20 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same
EP1180799A3 (en) * 2000-08-17 2005-09-28 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same
US7242608B2 (en) 2000-08-17 2007-07-10 Kabushiki Kaisha Toshiba Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers
US7257015B2 (en) 2000-08-17 2007-08-14 Kabushiki Kaisha Toshiba Semiconductor memory device having a floating storage bulk region
US7710785B2 (en) 2000-08-17 2010-05-04 Kabushiki Kaisha Toshiba Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers
US7855920B2 (en) 2000-08-17 2010-12-21 Kabushiki Kaisha Toshiba Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers

Also Published As

Publication number Publication date
JPS6410946B2 (en) 1989-02-22

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