JPS56117396A - Processor for waveform conversion - Google Patents
Processor for waveform conversionInfo
- Publication number
- JPS56117396A JPS56117396A JP2008780A JP2008780A JPS56117396A JP S56117396 A JPS56117396 A JP S56117396A JP 2008780 A JP2008780 A JP 2008780A JP 2008780 A JP2008780 A JP 2008780A JP S56117396 A JPS56117396 A JP S56117396A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- memory
- frequency
- beta
- conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Picture Signal Circuits (AREA)
Abstract
PURPOSE:To achieve storage to memory, by ensuring waveform and digital conversion with a simple constitution, through different clock frequency for charge transfer delay (CCD) write-in and readout and A/D conversion. CONSTITUTION:A TV vertical synchronizing signal is written in the CCD element 22 by using the 1st clock alpha in the frequency <=2 the video band. This signal is read out by using the clock beta lower in the frequency than the clock alpha, and it is converted with the A/D converter 23 the timing of which is controlled with the clock beta and written in the memory 24. Further, the memory 24 is read out with the clock gamma shifted with the same frequency as the clock beta. Thus, the conversion by the converter 23 and the write-in to the memory 24 are not necessary for real time operation, and malfunction due to deficient response speed of components is not caused, and the signal is surely in digital conversion with a simple constitution, allowing the processing via the memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008780A JPS56117396A (en) | 1980-02-20 | 1980-02-20 | Processor for waveform conversion |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008780A JPS56117396A (en) | 1980-02-20 | 1980-02-20 | Processor for waveform conversion |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56117396A true JPS56117396A (en) | 1981-09-14 |
Family
ID=12017317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008780A Pending JPS56117396A (en) | 1980-02-20 | 1980-02-20 | Processor for waveform conversion |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56117396A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02113497A (en) * | 1988-10-21 | 1990-04-25 | Mitsubishi Electric Corp | Storage device |
-
1980
- 1980-02-20 JP JP2008780A patent/JPS56117396A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02113497A (en) * | 1988-10-21 | 1990-04-25 | Mitsubishi Electric Corp | Storage device |
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