JPS5611683A - Control system for refresh read-in write-in - Google Patents

Control system for refresh read-in write-in

Info

Publication number
JPS5611683A
JPS5611683A JP8532979A JP8532979A JPS5611683A JP S5611683 A JPS5611683 A JP S5611683A JP 8532979 A JP8532979 A JP 8532979A JP 8532979 A JP8532979 A JP 8532979A JP S5611683 A JPS5611683 A JP S5611683A
Authority
JP
Japan
Prior art keywords
address
refresh
write
read
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8532979A
Other languages
Japanese (ja)
Other versions
JPS5918792B2 (en
Inventor
Masateru Tagami
Hiroshi Shinkawa
Naoaki Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP54085329A priority Critical patent/JPS5918792B2/en
Publication of JPS5611683A publication Critical patent/JPS5611683A/en
Publication of JPS5918792B2 publication Critical patent/JPS5918792B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Abstract

PURPOSE:To enable the read-in and write-in even at refresh cycle, by detecting the agreement with the refresh address and the designated address and accessing the dynamic memory with the designated address. CONSTITUTION:At refresh cycle, the output of the refresh address counter RFAC is fed to the dynamic memory MEM via the multiplexer MPX1 controlled with the control circuit CNTL as the row address for refresh. In this case, when the read-in address is set to the address register ADRR2 from the input control unit IOC, the row address and the content of the counter RFAC are fed to the comparison circuit MAT and if they are in agreement, the agreement signal is fed to the circuit CNTL. Then, the address set to the register ADRR2 accesses the memory MEM via the multiplexer MPX1 and the read-in by the designated address is made. This is the same for the write-in and read-in and write-in can be made during the refresh cycle.
JP54085329A 1979-07-05 1979-07-05 Refresh read/write control method Expired JPS5918792B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54085329A JPS5918792B2 (en) 1979-07-05 1979-07-05 Refresh read/write control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54085329A JPS5918792B2 (en) 1979-07-05 1979-07-05 Refresh read/write control method

Publications (2)

Publication Number Publication Date
JPS5611683A true JPS5611683A (en) 1981-02-05
JPS5918792B2 JPS5918792B2 (en) 1984-04-28

Family

ID=13855588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54085329A Expired JPS5918792B2 (en) 1979-07-05 1979-07-05 Refresh read/write control method

Country Status (1)

Country Link
JP (1) JPS5918792B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5295109A (en) * 1991-06-21 1994-03-15 Sharp Kabushiki Kaisha Semiconductor memory

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61202333U (en) * 1985-06-07 1986-12-19
JPH0199897U (en) * 1987-12-23 1989-07-04

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5295109A (en) * 1991-06-21 1994-03-15 Sharp Kabushiki Kaisha Semiconductor memory

Also Published As

Publication number Publication date
JPS5918792B2 (en) 1984-04-28

Similar Documents

Publication Publication Date Title
JPS5438724A (en) Display unit
JPS6446293A (en) Scanning tester for digital system with dynamic random access memory
JPS5611683A (en) Control system for refresh read-in write-in
JPS5454531A (en) Crt display unti
JPS5668990A (en) Memory circuit
KR910006831A (en) Controller for connecting peripheral devices with microcomputer
JPS5447438A (en) Control system for scratch memory
JPS558615A (en) Refresh control system
JPS56168256A (en) Data processor
JPS5445550A (en) Digital protection control unit
JPS5443643A (en) Control storage unit
JPS5491151A (en) Internal memory control system on array processor
KR920004414B1 (en) Communication method between processor and coprocessor
JPS54141536A (en) Information processing system
JPS53118939A (en) Display unit
JPS5451433A (en) Data processing system
JPS5464935A (en) Transfer control device
JPS5425642A (en) Input and output control system
KR940006298Y1 (en) Dual memory interface unit
JPS5686573A (en) Reader
JPS578980A (en) Memory device
JPS5611534A (en) Direct memory access transfer control system
JPS5447445A (en) Memory unit
JPS564825A (en) Pulse input unit
JPS55104116A (en) Tap control circuit of individual write-in ram system