JPS56111351A - Synchronization system - Google Patents
Synchronization systemInfo
- Publication number
- JPS56111351A JPS56111351A JP1420680A JP1420680A JPS56111351A JP S56111351 A JPS56111351 A JP S56111351A JP 1420680 A JP1420680 A JP 1420680A JP 1420680 A JP1420680 A JP 1420680A JP S56111351 A JPS56111351 A JP S56111351A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- synchronizing
- diffusion
- band
- detector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To realize brief and stable synchronization by performing diffusion modulation with wide-band diffusion codes and by separating respective circuits while sharing the same frequency band. CONSTITUTION:A received signal (Rx Signal) is passed through an antenna and high-frequency amplifier and then converted by mixer 21 into an intermediate- frequency signal. A synchronizing signal, included in the received signal, is separated from a diffusion information signal by narrow-band filter 22, amplified by amplifier 23 and phase-synchronously detected by synchronous detector 25 to be extracted as the synchronizing signal. The output of this detector 25 is applied to multiplier 26 to generate the bit-synchronizing clock of diffused codes and while the clock tracking loop consisting of position detector 27 and VCO28 is controlled, controller 30 which controls the start of reverse diffusing code generator 29 is controlled. Consequently, the synchronized signal is correlatively detected by the correlator composed of multiplier 31, etc., and demodulated by demodulator 34 to a high-pitched tone.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1420680A JPS56111351A (en) | 1980-02-07 | 1980-02-07 | Synchronization system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1420680A JPS56111351A (en) | 1980-02-07 | 1980-02-07 | Synchronization system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56111351A true JPS56111351A (en) | 1981-09-03 |
Family
ID=11854626
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1420680A Pending JPS56111351A (en) | 1980-02-07 | 1980-02-07 | Synchronization system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56111351A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021245718A1 (en) * | 2020-05-30 | 2021-12-09 | 公立大学法人公立諏訪東京理科大学 | Wireless transmission method |
-
1980
- 1980-02-07 JP JP1420680A patent/JPS56111351A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021245718A1 (en) * | 2020-05-30 | 2021-12-09 | 公立大学法人公立諏訪東京理科大学 | Wireless transmission method |
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