JPS5610955A - Semiconductor memory - Google Patents
Semiconductor memoryInfo
- Publication number
- JPS5610955A JPS5610955A JP8716579A JP8716579A JPS5610955A JP S5610955 A JPS5610955 A JP S5610955A JP 8716579 A JP8716579 A JP 8716579A JP 8716579 A JP8716579 A JP 8716579A JP S5610955 A JPS5610955 A JP S5610955A
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- minority carrier
- channel
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 abstract 4
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Landscapes
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To contrive the extension of a memory retaining time of a semiconductor memory by forming a reverse conducting type diffused layer to a substrate between a memory cell and a carrier discharge source and applying prescribed constant voltage thereto to absorb minority carrier to the layer. CONSTITUTION:A reverse polarity diffused layer 3 to a substrate is disposed between a memory cell 1 and a bootstrap circuit 2.The circuit 2 is an electron minority carrier discharge source in an N-channel and a hole minority carrier discharge source in a P-channel.The layer 3 is connected at the positions 5 to wiring layers 4, and a power supply voltage VDD is applied thereto. A constant voltage higher than the substrate is applied when the memory cell is N-channel, while the constant voltage lower than the substrate is applied when the memory cell is P-channel. Since the layer 3 absorbes the minority carrier to reduce the minority carrier reaching the memory cell 1 from the circuit 2 according to this configuration, it can extend the memory retaining time. It can also shorten the distance between the cell 1 and the source 2 so as to reduce the size thereof.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8716579A JPS5610955A (en) | 1979-07-09 | 1979-07-09 | Semiconductor memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8716579A JPS5610955A (en) | 1979-07-09 | 1979-07-09 | Semiconductor memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5610955A true JPS5610955A (en) | 1981-02-03 |
Family
ID=13907368
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8716579A Pending JPS5610955A (en) | 1979-07-09 | 1979-07-09 | Semiconductor memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5610955A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60198772A (en) * | 1984-03-22 | 1985-10-08 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated device |
JPH01231539A (en) * | 1988-03-11 | 1989-09-14 | Hitachi Ltd | Multi-point terminal system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5068483A (en) * | 1973-10-19 | 1975-06-07 |
-
1979
- 1979-07-09 JP JP8716579A patent/JPS5610955A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5068483A (en) * | 1973-10-19 | 1975-06-07 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60198772A (en) * | 1984-03-22 | 1985-10-08 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated device |
JPH01231539A (en) * | 1988-03-11 | 1989-09-14 | Hitachi Ltd | Multi-point terminal system |
JPH0683219B2 (en) * | 1988-03-11 | 1994-10-19 | 株式会社日立製作所 | Multipoint terminal system |
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