JPS5610755A - Synchronizing system - Google Patents

Synchronizing system

Info

Publication number
JPS5610755A
JPS5610755A JP8708079A JP8708079A JPS5610755A JP S5610755 A JPS5610755 A JP S5610755A JP 8708079 A JP8708079 A JP 8708079A JP 8708079 A JP8708079 A JP 8708079A JP S5610755 A JPS5610755 A JP S5610755A
Authority
JP
Japan
Prior art keywords
time
signals
timing
intra
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8708079A
Other languages
Japanese (ja)
Other versions
JPS603251B2 (en
Inventor
Junzo Hirano
Yukio Inoue
Tokuhiro Kitami
Hideo Kuroda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54087080A priority Critical patent/JPS603251B2/en
Publication of JPS5610755A publication Critical patent/JPS5610755A/en
Publication of JPS603251B2 publication Critical patent/JPS603251B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To obtain the time-division multiplied signals in the different timing relations and in the easy and steady way, by delivering the signal synchronized with the intra-office unified frame timing from the two memories which switch and store the digital signals of the time-division multiplied signals. CONSTITUTION:The time-division multiplied signals sent from incoming line HWI and equivalent to at least one frame are applied to one side of memories FM-A and FM-B each via switching circuit SW-1. And the digital signal of the time-division multiplied signal is stored successively into the address having the same number as the time slot number of the digital signal. At the same time, the signals showing the time slot synchronized with both the intra-office unified bit timing and the frame timing are applied to the other side of memories FM-A and FM-B each from timing signal generator TPG and in the form of the address designating signals. As a result, the digital signal synchronized with the intra-office unified framing is sent to outgoing line HWO. Thus time-division multiplied signals in the different timing relations can be obtained easily and steadily and in the simple constitution.
JP54087080A 1979-07-09 1979-07-09 Synchronization method Expired JPS603251B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54087080A JPS603251B2 (en) 1979-07-09 1979-07-09 Synchronization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54087080A JPS603251B2 (en) 1979-07-09 1979-07-09 Synchronization method

Publications (2)

Publication Number Publication Date
JPS5610755A true JPS5610755A (en) 1981-02-03
JPS603251B2 JPS603251B2 (en) 1985-01-26

Family

ID=13904959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54087080A Expired JPS603251B2 (en) 1979-07-09 1979-07-09 Synchronization method

Country Status (1)

Country Link
JP (1) JPS603251B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0195478A2 (en) * 1985-03-16 1986-09-24 Philips Patentverwaltung GmbH Method and circuit for the switching without fase jumps of broad-band digital signals in a synchronous broad-band communication network
JPS647827A (en) * 1987-06-30 1989-01-11 Nec Corp Radio transmission base station
JPH0279394A (en) * 1988-07-27 1990-03-19 General Electric Co (Ge) Parallel arrangement type starting circuit for gas discharge lamp
JPH0290834A (en) * 1988-09-28 1990-03-30 Hitachi Ltd Atm channel equipment and atm line terminal equipment
JPH02226930A (en) * 1989-02-28 1990-09-10 Meidensha Corp Transmission delay phase compensation circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0195478A2 (en) * 1985-03-16 1986-09-24 Philips Patentverwaltung GmbH Method and circuit for the switching without fase jumps of broad-band digital signals in a synchronous broad-band communication network
JPS647827A (en) * 1987-06-30 1989-01-11 Nec Corp Radio transmission base station
JPH0279394A (en) * 1988-07-27 1990-03-19 General Electric Co (Ge) Parallel arrangement type starting circuit for gas discharge lamp
JPH0290834A (en) * 1988-09-28 1990-03-30 Hitachi Ltd Atm channel equipment and atm line terminal equipment
JPH02226930A (en) * 1989-02-28 1990-09-10 Meidensha Corp Transmission delay phase compensation circuit

Also Published As

Publication number Publication date
JPS603251B2 (en) 1985-01-26

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