JPS56105538A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS56105538A
JPS56105538A JP749880A JP749880A JPS56105538A JP S56105538 A JPS56105538 A JP S56105538A JP 749880 A JP749880 A JP 749880A JP 749880 A JP749880 A JP 749880A JP S56105538 A JPS56105538 A JP S56105538A
Authority
JP
Japan
Prior art keywords
data
register
signal
cpu1
operator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP749880A
Other languages
Japanese (ja)
Inventor
Haruhiko Tomono
Yasuyuki Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP749880A priority Critical patent/JPS56105538A/en
Publication of JPS56105538A publication Critical patent/JPS56105538A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)

Abstract

PURPOSE:To enable moving data to be logically operated by reading out the data to be moved from an RAM through controlling of a direct memory access DMA controller and performing desired arithmetic processing with an operator. CONSTITUTION:When a holding signal 11 is inputted from a DMA controller CT2 to a CPU1, the answer signal 19 is returned from the CPU1 to the CT2, and the CT2 holds the initiative of system controlling. The control signal from the CPU1 is stored in a control register 3, and the CT2 is started by this signal. The data to be moved are read out from an RAM6 by controlling of the CT2, and the read-out data are stored in an input register 5. The data stored in the register 5 are inputted to an operator 4 by the control signal of the CT2. The operator 4 makes the desired logic operation of the input data by the control signal of the register 3 and writes the results thereof into another region of the RAM6. Thereby, the high-speed data transmission is executed by the CT2 and the logic operation is executed for the transferred data.
JP749880A 1980-01-25 1980-01-25 Data processing device Pending JPS56105538A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP749880A JPS56105538A (en) 1980-01-25 1980-01-25 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP749880A JPS56105538A (en) 1980-01-25 1980-01-25 Data processing device

Publications (1)

Publication Number Publication Date
JPS56105538A true JPS56105538A (en) 1981-08-22

Family

ID=11667435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP749880A Pending JPS56105538A (en) 1980-01-25 1980-01-25 Data processing device

Country Status (1)

Country Link
JP (1) JPS56105538A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228582A (en) * 1985-04-02 1986-10-11 Sharp Corp Picture processor
JPS61233869A (en) * 1985-04-08 1986-10-18 Sharp Corp Picture processor
JPS6244350U (en) * 1985-08-31 1987-03-17
JPH09138761A (en) * 1996-11-18 1997-05-27 Hitachi Ltd One chip memory device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51101435A (en) * 1975-03-04 1976-09-07 Hitachi Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51101435A (en) * 1975-03-04 1976-09-07 Hitachi Ltd

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228582A (en) * 1985-04-02 1986-10-11 Sharp Corp Picture processor
JPS61233869A (en) * 1985-04-08 1986-10-18 Sharp Corp Picture processor
JPS6244350U (en) * 1985-08-31 1987-03-17
JPH09138761A (en) * 1996-11-18 1997-05-27 Hitachi Ltd One chip memory device

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