JPS56102157A - Memory device of facsimile device - Google Patents
Memory device of facsimile deviceInfo
- Publication number
- JPS56102157A JPS56102157A JP361080A JP361080A JPS56102157A JP S56102157 A JPS56102157 A JP S56102157A JP 361080 A JP361080 A JP 361080A JP 361080 A JP361080 A JP 361080A JP S56102157 A JPS56102157 A JP S56102157A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- dummy
- memory
- picture signal
- sign
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Storing Facsimile Image Data (AREA)
Abstract
PURPOSE:To increase the use efficiency of a memory device and simplify its detection circuits by arranging the detection circuit detecting synchornous codes and dummy signs to the I/O circuit of the memory device. CONSTITUTION:When a picture signal is stored in memory 10, received data and clocks are selected by the 1st multiplexer 7 and the selected data and clock are applied to synchronous code and dummy sign detection circuit 11 through the 1st shift register 8 to check the output pattern. When a synchronous code is detected, the 1st latch 9 fetches the syncyronous code and the 1st bit counter 12 starts to count. When a dummy sign is detected, counter 12 stops counting and removes the dummy part to write the picture signal in memory 10. When the picture signal is sent from memory 10, the output from the 2nd shift register 14 is transferred to dummy sign adding circuit 15, the sign data and cock outputted from register 14 are selected by multiplexer 7 and added to register 8, synchronization with transmitted data TVD is detected by circuit 11 and the picture signal is sent from circuit 15 by the control of system control circuit 19.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP361080A JPS56102157A (en) | 1980-01-18 | 1980-01-18 | Memory device of facsimile device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP361080A JPS56102157A (en) | 1980-01-18 | 1980-01-18 | Memory device of facsimile device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56102157A true JPS56102157A (en) | 1981-08-15 |
Family
ID=11562251
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP361080A Pending JPS56102157A (en) | 1980-01-18 | 1980-01-18 | Memory device of facsimile device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56102157A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0593167U (en) * | 1985-07-15 | 1993-12-17 | クローネ アクチエンゲゼルシャフト | Video video signal clock pulse adjustment device |
-
1980
- 1980-01-18 JP JP361080A patent/JPS56102157A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0593167U (en) * | 1985-07-15 | 1993-12-17 | クローネ アクチエンゲゼルシャフト | Video video signal clock pulse adjustment device |
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