JPS5599777A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5599777A
JPS5599777A JP711179A JP711179A JPS5599777A JP S5599777 A JPS5599777 A JP S5599777A JP 711179 A JP711179 A JP 711179A JP 711179 A JP711179 A JP 711179A JP S5599777 A JPS5599777 A JP S5599777A
Authority
JP
Japan
Prior art keywords
layer
silicon
poly
contact
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP711179A
Other languages
Japanese (ja)
Inventor
Kenjiro Yasunari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP711179A priority Critical patent/JPS5599777A/en
Publication of JPS5599777A publication Critical patent/JPS5599777A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To achieve high-density integration without increasing working processes, by forming a contact of a drain or source region by using the 2nd layer silicon other than a gate wiring.
CONSTITUTION: First, the process of forming rate insulating silicon oxide film 16 on the surface of a substrate is completed. Next, after the 1st layer poly-silicon being deposited on film 16, gate forming poly-silicon layer 40 of pattern 40 is formed. By using layer 40 as a mask, N+-type source region 44 and an N+-type drain region are formed. Next, etched part 50, including a contact hole, is formed. Then, after the 2nd layer poly-silicon being deposited on the upper surface of the substrate by the CVD method, source-wiring and capacitor-electrode-forming poly-silicon layers 52A and 52B are formed by using patterns 52A and 52B. Layers 52A and 52B are made low resistance layers by doping them with a high concentration donor impurity, and at the same time, corresonding to the contact hole of etched part 50, N+-type contact region 54 is formed. By this, it makes unnecessary to provide a separation gap between the contact part of layer 52A and film 16.
COPYRIGHT: (C)1980,JPO&Japio
JP711179A 1979-01-26 1979-01-26 Manufacture of semiconductor device Pending JPS5599777A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP711179A JPS5599777A (en) 1979-01-26 1979-01-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP711179A JPS5599777A (en) 1979-01-26 1979-01-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5599777A true JPS5599777A (en) 1980-07-30

Family

ID=11656969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP711179A Pending JPS5599777A (en) 1979-01-26 1979-01-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5599777A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006281160A (en) * 2005-04-04 2006-10-19 Takuma Co Ltd Waste sorting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006281160A (en) * 2005-04-04 2006-10-19 Takuma Co Ltd Waste sorting device

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