JPS5583333A - D-type latch circuit - Google Patents

D-type latch circuit

Info

Publication number
JPS5583333A
JPS5583333A JP16045778A JP16045778A JPS5583333A JP S5583333 A JPS5583333 A JP S5583333A JP 16045778 A JP16045778 A JP 16045778A JP 16045778 A JP16045778 A JP 16045778A JP S5583333 A JPS5583333 A JP S5583333A
Authority
JP
Japan
Prior art keywords
terminal
data
conducts
gets cut
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16045778A
Other languages
Japanese (ja)
Inventor
Toshiaki Wakita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Takeda Riken Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp, Takeda Riken Industries Co Ltd filed Critical Advantest Corp
Priority to JP16045778A priority Critical patent/JPS5583333A/en
Publication of JPS5583333A publication Critical patent/JPS5583333A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
    • H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To make it possible to obtain invariably-constant set-up time without reference to a previous state, by connecting the common current path of FF to the other output side of a current change-over switch. CONSTITUTION:Once a clock pulse is supplied to terminal 16, transistor Tr12 conducts to activate differential type comparator circuit 18. When the data of input terminal 23 is higher than the comparison voltage of terminal 24, Tr21 and Tr22 are ON and OFF respectively, and output terminals 36 and 37 are held at high and low level respectively. On the other hand, since Tr13 is OFF, Trs 28 and 29 are both OFF and a state bearing no relation to the latch state of previous data is set. After a clock pulse falls, Tr13 conducts with a little bit delay and Tr12 gets cut off, so that a common emitter current of Tr21 and Tr22 will be switched to that of Tr28 and Tr29. For example, if Tr21 is ON, Tr28 gets cut off and even when Tr22 is OFF, Tr29 also gets cut off. In this way, the data of terminal 23 is latched by FF25.
JP16045778A 1978-12-20 1978-12-20 D-type latch circuit Pending JPS5583333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16045778A JPS5583333A (en) 1978-12-20 1978-12-20 D-type latch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16045778A JPS5583333A (en) 1978-12-20 1978-12-20 D-type latch circuit

Publications (1)

Publication Number Publication Date
JPS5583333A true JPS5583333A (en) 1980-06-23

Family

ID=15715343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16045778A Pending JPS5583333A (en) 1978-12-20 1978-12-20 D-type latch circuit

Country Status (1)

Country Link
JP (1) JPS5583333A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532440A (en) * 1981-12-01 1985-07-30 Siemens Aktiengesellschaft Flip-flop in current mode logic controlled by a transfer clock with auxiliary current applied to differential amplifier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5145974U (en) * 1974-10-02 1976-04-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5145974U (en) * 1974-10-02 1976-04-05

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532440A (en) * 1981-12-01 1985-07-30 Siemens Aktiengesellschaft Flip-flop in current mode logic controlled by a transfer clock with auxiliary current applied to differential amplifier

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