JPS5582349A - Display control system - Google Patents

Display control system

Info

Publication number
JPS5582349A
JPS5582349A JP15583278A JP15583278A JPS5582349A JP S5582349 A JPS5582349 A JP S5582349A JP 15583278 A JP15583278 A JP 15583278A JP 15583278 A JP15583278 A JP 15583278A JP S5582349 A JPS5582349 A JP S5582349A
Authority
JP
Japan
Prior art keywords
display control
value
address
microprocessor
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15583278A
Other languages
Japanese (ja)
Inventor
Juichi Sakai
Toshiharu Kaizawa
Shogo Takayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15583278A priority Critical patent/JPS5582349A/en
Publication of JPS5582349A publication Critical patent/JPS5582349A/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To shorten a processing time to improve the processing capability of display control by setting the read start address of a screen buffer to an arbitrary address by a microprocessor.
CONSTITUTION: The value of register 30 is set to A by microprocessor 41, and simultaneously, the value of this register 30 is transferred to address counter 31. Next, the value of counter 31 is counted up in order of A, A+n, A+2n,...A+23h, and simultaneously, read start addresses of screen buffer 10 based on these values are set to arbitrary addresses from memory 42 to write data codes. These data codes are converted to dot patterns successively by character generator 43 and are subjected to parallel-series conversion by parallel-series converter 44 and are displayed on display equipment 20'. As a result, the processing time can be shortened to improve the processing capability of display control.
COPYRIGHT: (C)1980,JPO&Japio
JP15583278A 1978-12-19 1978-12-19 Display control system Pending JPS5582349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15583278A JPS5582349A (en) 1978-12-19 1978-12-19 Display control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15583278A JPS5582349A (en) 1978-12-19 1978-12-19 Display control system

Publications (1)

Publication Number Publication Date
JPS5582349A true JPS5582349A (en) 1980-06-21

Family

ID=15614463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15583278A Pending JPS5582349A (en) 1978-12-19 1978-12-19 Display control system

Country Status (1)

Country Link
JP (1) JPS5582349A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224822A (en) * 1986-03-26 1987-10-02 Hitachi Ltd Display controller
CN111701254A (en) * 2020-08-18 2020-09-25 北京理工大学 Parallel acceleration display method for large-scale performance dynamic stage video

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62224822A (en) * 1986-03-26 1987-10-02 Hitachi Ltd Display controller
CN111701254A (en) * 2020-08-18 2020-09-25 北京理工大学 Parallel acceleration display method for large-scale performance dynamic stage video

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