JPS5580333A - Manufacture of mos semiconductor device - Google Patents

Manufacture of mos semiconductor device

Info

Publication number
JPS5580333A
JPS5580333A JP15355078A JP15355078A JPS5580333A JP S5580333 A JPS5580333 A JP S5580333A JP 15355078 A JP15355078 A JP 15355078A JP 15355078 A JP15355078 A JP 15355078A JP S5580333 A JPS5580333 A JP S5580333A
Authority
JP
Japan
Prior art keywords
film
layer
island
sio
islands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15355078A
Other languages
Japanese (ja)
Other versions
JPS616548B2 (en
Inventor
Takeshi Tokuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15355078A priority Critical patent/JPS5580333A/en
Publication of JPS5580333A publication Critical patent/JPS5580333A/en
Publication of JPS616548B2 publication Critical patent/JPS616548B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To prevent interleakage by the structure such that an Si-layer is grown on an insulation substrate, this is oxidized by using SiO2 film and Si3N4 film as mask, the Si-layer is divided into two islands with their ends made smooth, and a MOS element is formed on each.
CONSTITUTION: Intrinsic Si-layer 2 is grown on sapphire substrate 1, and a laminate of SiO2 film 17 and Si3N4 film 18 is coated on the entire surface. Only film 18 is removed partially by etching it with resist fim 19 used as mask. Next, film 19 is removed. By operating heat treatment, layer 2, including the exposed part of film 17, is converted into thick SiO2 film reaching substrate 1. Film 18 is removed. By this, layer 2 is divided by film 10 into two islands 2a and 2b with their ends made smooth. Island 2b is covered with resist film 21, and island 2a is injected with ions, and thereby the specified conduction type is obtained. Subsequently, film 21 is removed, and source-drain region 3, gate oxide film 4, gate electrode 5, etc. are formed on each island.
COPYRIGHT: (C)1980,JPO&Japio
JP15355078A 1978-12-11 1978-12-11 Manufacture of mos semiconductor device Granted JPS5580333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15355078A JPS5580333A (en) 1978-12-11 1978-12-11 Manufacture of mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15355078A JPS5580333A (en) 1978-12-11 1978-12-11 Manufacture of mos semiconductor device

Publications (2)

Publication Number Publication Date
JPS5580333A true JPS5580333A (en) 1980-06-17
JPS616548B2 JPS616548B2 (en) 1986-02-27

Family

ID=15564951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15355078A Granted JPS5580333A (en) 1978-12-11 1978-12-11 Manufacture of mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5580333A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0215643U (en) * 1988-07-14 1990-01-31

Also Published As

Publication number Publication date
JPS616548B2 (en) 1986-02-27

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