JPS5579527A - Pulse width converter - Google Patents

Pulse width converter

Info

Publication number
JPS5579527A
JPS5579527A JP15389578A JP15389578A JPS5579527A JP S5579527 A JPS5579527 A JP S5579527A JP 15389578 A JP15389578 A JP 15389578A JP 15389578 A JP15389578 A JP 15389578A JP S5579527 A JPS5579527 A JP S5579527A
Authority
JP
Japan
Prior art keywords
pulse
pulses
gate
terminal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15389578A
Other languages
Japanese (ja)
Inventor
Yuichi Shiotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15389578A priority Critical patent/JPS5579527A/en
Publication of JPS5579527A publication Critical patent/JPS5579527A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE: To convert input pulses of random width into output pulses of constant width by generating pulses synchronizing with pulses, obtained by dividing high- frequency clock pulses by input pulses, and clock pulses.
CONSTITUTION: Clock pulses B are applied to terminal 1, and input pulse A is to terminal 2; and FF7 is set at a fall of pulse B right after pulse A and gate pulse C is outputted from terminal Q' and then inputted to gate 6. Gate 6 performs the logical sum of pulses A and B to generate set pulse D, thereby resetting FFa 4 and 5 of divider circuit 3. Circuit 3 starts dividing pulse B and FFs 4 and 5 generate division outputs E and F. After three pulses B from the leading edge of pulse D are divided, gate 9 generates reset pulse G. Pulse D from gate 6 sets FF8 and pulse G from gate 9 resets it, so that output pulse H of constant pulse width equivalent to three pulses B can be obtained from FF8 at any time.
COPYRIGHT: (C)1980,JPO&Japio
JP15389578A 1978-12-12 1978-12-12 Pulse width converter Pending JPS5579527A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15389578A JPS5579527A (en) 1978-12-12 1978-12-12 Pulse width converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15389578A JPS5579527A (en) 1978-12-12 1978-12-12 Pulse width converter

Publications (1)

Publication Number Publication Date
JPS5579527A true JPS5579527A (en) 1980-06-16

Family

ID=15572448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15389578A Pending JPS5579527A (en) 1978-12-12 1978-12-12 Pulse width converter

Country Status (1)

Country Link
JP (1) JPS5579527A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818274A (en) * 1995-11-07 1998-10-06 Sgs-Thomson Microelectronics S.R.L. Flip-flop circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4949524A (en) * 1972-09-14 1974-05-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4949524A (en) * 1972-09-14 1974-05-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818274A (en) * 1995-11-07 1998-10-06 Sgs-Thomson Microelectronics S.R.L. Flip-flop circuit

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