JPS5572260A - Input-output device - Google Patents

Input-output device

Info

Publication number
JPS5572260A
JPS5572260A JP14576178A JP14576178A JPS5572260A JP S5572260 A JPS5572260 A JP S5572260A JP 14576178 A JP14576178 A JP 14576178A JP 14576178 A JP14576178 A JP 14576178A JP S5572260 A JPS5572260 A JP S5572260A
Authority
JP
Japan
Prior art keywords
input
cpu
hot
line replacement
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14576178A
Other languages
Japanese (ja)
Inventor
Yukio Urushibata
Osamu Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14576178A priority Critical patent/JPS5572260A/en
Publication of JPS5572260A publication Critical patent/JPS5572260A/en
Pending legal-status Critical Current

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  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To prevent an error signal from being generated due to hot-line replacement in case that an input-output board connected to an input-output controller is in process of hot-line replacement, by providing the input-output controller with a switch method.
CONSTITUTION: When CPU sends a signal for the selective assignment of input-output board 3i to input-output controller IOC2i, error detection circuit 101 detects the absence of 3i, if so, and sends only error signal ERR to CPU. When 3i is in process of hot-line replacement, switch 102 outputs signal "1" and gate circuit 103 sends out AND output OEX of this signal "1" and error signal ERR to CPU, so that CPU can detect 3i being in process of hot-line replacement by receiving both ERR and OEX signals. Consequently, CPU assigns selectively 3i again after-ward.
COPYRIGHT: (C)1980,JPO&Japio
JP14576178A 1978-11-25 1978-11-25 Input-output device Pending JPS5572260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14576178A JPS5572260A (en) 1978-11-25 1978-11-25 Input-output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14576178A JPS5572260A (en) 1978-11-25 1978-11-25 Input-output device

Publications (1)

Publication Number Publication Date
JPS5572260A true JPS5572260A (en) 1980-05-30

Family

ID=15392541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14576178A Pending JPS5572260A (en) 1978-11-25 1978-11-25 Input-output device

Country Status (1)

Country Link
JP (1) JPS5572260A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8352661B1 (en) * 2010-03-24 2013-01-08 Emc Corporation Data storage systems having seamless software upgrades

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8352661B1 (en) * 2010-03-24 2013-01-08 Emc Corporation Data storage systems having seamless software upgrades

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