JPS5570757A - Logical test unit for integrated circuit - Google Patents

Logical test unit for integrated circuit

Info

Publication number
JPS5570757A
JPS5570757A JP14355778A JP14355778A JPS5570757A JP S5570757 A JPS5570757 A JP S5570757A JP 14355778 A JP14355778 A JP 14355778A JP 14355778 A JP14355778 A JP 14355778A JP S5570757 A JPS5570757 A JP S5570757A
Authority
JP
Japan
Prior art keywords
signal
cpu1
circuit
skew
tested
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14355778A
Other languages
Japanese (ja)
Other versions
JPS6222103B2 (en
Inventor
Katsuhiko Takeda
Shinji Hiratsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi High Tech Corp
Original Assignee
Hitachi Ltd
Hitachi Electronics Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Electronics Engineering Co Ltd filed Critical Hitachi Ltd
Priority to JP14355778A priority Critical patent/JPS5570757A/en
Publication of JPS5570757A publication Critical patent/JPS5570757A/en
Publication of JPS6222103B2 publication Critical patent/JPS6222103B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE: To automatically perform skew correction for test signal based on the data, by comparing the test signal fed to the tested IC with the reference signal and calculating and storing the data for required correction for skew correction with CPU.
CONSTITUTION: After the test signal d delivered from the pattern generator in CPU1 is received at the line receiver circuit 14, it is converted into the negative polarity signal e at the pulse polarity conversion circuit 20 and inputted to the leading skew correction circuit 9 and trailing skew correction circuit 10. Further, the reference pulse from the reference pulse forming circuit 19 is compared with the designated reference signal v with the reference pulse designation signal w from CPU1 to discriminate the skew and the skew discrimination designation signal n is fed to CPU1. Thus, the test signal k is fed at the tested ICg and after the logic operation, the output signal p is delivered. Afther this signal p is confirmed for the specified level at the receive pulse discrimination circuit 16, and it is transferred to CPU1 as the discriminated output signal r. This signal is compared with the expected pattern signal at CPU1 to discriminate the propriety of the tested IC8.
COPYRIGHT: (C)1980,JPO&Japio
JP14355778A 1978-11-22 1978-11-22 Logical test unit for integrated circuit Granted JPS5570757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14355778A JPS5570757A (en) 1978-11-22 1978-11-22 Logical test unit for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14355778A JPS5570757A (en) 1978-11-22 1978-11-22 Logical test unit for integrated circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP63028669A Division JPS63302380A (en) 1988-02-12 1988-02-12 Logical test apparatus for integrated circuit

Publications (2)

Publication Number Publication Date
JPS5570757A true JPS5570757A (en) 1980-05-28
JPS6222103B2 JPS6222103B2 (en) 1987-05-15

Family

ID=15341502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14355778A Granted JPS5570757A (en) 1978-11-22 1978-11-22 Logical test unit for integrated circuit

Country Status (1)

Country Link
JP (1) JPS5570757A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57111472A (en) * 1980-12-29 1982-07-10 Advantest Corp Logical-circuit testing device
JPS60193356A (en) * 1984-03-14 1985-10-01 Mitsubishi Electric Corp Timing compensator for semiconductor inspecting device
JPS61286768A (en) * 1985-06-13 1986-12-17 Hitachi Ltd Test apparatus
JPS63302380A (en) * 1988-02-12 1988-12-09 Hitachi Ltd Logical test apparatus for integrated circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02299908A (en) * 1989-05-15 1990-12-12 Bridgestone Corp Pneumatic tire provided with directional tread

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57111472A (en) * 1980-12-29 1982-07-10 Advantest Corp Logical-circuit testing device
JPS60193356A (en) * 1984-03-14 1985-10-01 Mitsubishi Electric Corp Timing compensator for semiconductor inspecting device
JPS61286768A (en) * 1985-06-13 1986-12-17 Hitachi Ltd Test apparatus
JPS63302380A (en) * 1988-02-12 1988-12-09 Hitachi Ltd Logical test apparatus for integrated circuit

Also Published As

Publication number Publication date
JPS6222103B2 (en) 1987-05-15

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