JPS556875A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS556875A
JPS556875A JP7954478A JP7954478A JPS556875A JP S556875 A JPS556875 A JP S556875A JP 7954478 A JP7954478 A JP 7954478A JP 7954478 A JP7954478 A JP 7954478A JP S556875 A JPS556875 A JP S556875A
Authority
JP
Japan
Prior art keywords
insulating film
film
junction
depletion layer
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7954478A
Other languages
Japanese (ja)
Inventor
Kazuko Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7954478A priority Critical patent/JPS556875A/en
Publication of JPS556875A publication Critical patent/JPS556875A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain a stable high resisting-pressure element, by avoiding adverse effects on a flank due to cutting, etc. by suppressing the undesirable extent of a depletion layer by using glass with minus charge in a film, which can easily extend the depletion layer, as the protective film. CONSTITUTION:An end surface of a PN junction 3 formed by diffusing P type impurities on a N type substrate 1 is protected by means of an insulating film 4. The insulating film 4 is a glass insulating film that lead system glass powder is sticked and is made up by means of burning fusion. A metallic film 6 with strong reducing power is mounted on the insulating film 4 of circumferential portions outer than a junction end so as to surround the junction 3. Since minus charge is effectively induced to a P type substrate 1 under the insulating film 4, to which the metallic film 6 is evaporated, and fulfills its duties as a channel stopper, the extension of a depletion layer is obstructed, thus obtaining a stable high resisting-pressure element.
JP7954478A 1978-06-29 1978-06-29 Semiconductor device Pending JPS556875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7954478A JPS556875A (en) 1978-06-29 1978-06-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7954478A JPS556875A (en) 1978-06-29 1978-06-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS556875A true JPS556875A (en) 1980-01-18

Family

ID=13692930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7954478A Pending JPS556875A (en) 1978-06-29 1978-06-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS556875A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6070761A (en) * 1983-09-27 1985-04-22 Shindengen Electric Mfg Co Ltd Semiconductor device
US6670688B2 (en) 2001-08-22 2003-12-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including at least one schottky metal layer surrounding PN junction
US10347874B2 (en) 2010-04-07 2019-07-09 Murata Manufacturing Co., Ltd. Battery pack and method for making same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6070761A (en) * 1983-09-27 1985-04-22 Shindengen Electric Mfg Co Ltd Semiconductor device
US6670688B2 (en) 2001-08-22 2003-12-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including at least one schottky metal layer surrounding PN junction
US10347874B2 (en) 2010-04-07 2019-07-09 Murata Manufacturing Co., Ltd. Battery pack and method for making same

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