JPS5564682A - Buffer block return control system - Google Patents

Buffer block return control system

Info

Publication number
JPS5564682A
JPS5564682A JP13829478A JP13829478A JPS5564682A JP S5564682 A JPS5564682 A JP S5564682A JP 13829478 A JP13829478 A JP 13829478A JP 13829478 A JP13829478 A JP 13829478A JP S5564682 A JPS5564682 A JP S5564682A
Authority
JP
Japan
Prior art keywords
empty
blocks
buffer
address information
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13829478A
Other languages
Japanese (ja)
Other versions
JPS5931741B2 (en
Inventor
Tatsuo Suga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53138294A priority Critical patent/JPS5931741B2/en
Publication of JPS5564682A publication Critical patent/JPS5564682A/en
Publication of JPS5931741B2 publication Critical patent/JPS5931741B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To simplify a return process by providing a buffer block control table which provides the linear control of empty buffer blocks and full buffer blocks.
CONSTITUTION: To address part 7 in empty block control region 6-0 of buffer block control table 5, next address information of external memory unit 2 is set and to address part 8, address information of a terminal buffer block is set while the number of empty blocks is set to number part 9. Then, next address information is set to empty address parts 10-3, 10-6 and 10-1 of corresponding regions 6-3, 6-6 and 6-1 of empty buffer blocks 3-3, 3-6 and 3-1. On the other hand, next address information is set to next address parts 10-2, 10-4 and 10-5 of corresponding blocks 6-2, 6-4 and 6-5 of full buffer blocks 3-2, 3-4 and 3-5. To return blocks 3-2, 3-4 and 3-5, contents of address part 8 and number part 9 are rewritten and address information of initial full block 3-2 is set to the next address part of corresponding area 6-1 of a terminal empty block.
COPYRIGHT: (C)1980,JPO&Japio
JP53138294A 1978-11-09 1978-11-09 Buffer block return control method Expired JPS5931741B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53138294A JPS5931741B2 (en) 1978-11-09 1978-11-09 Buffer block return control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53138294A JPS5931741B2 (en) 1978-11-09 1978-11-09 Buffer block return control method

Publications (2)

Publication Number Publication Date
JPS5564682A true JPS5564682A (en) 1980-05-15
JPS5931741B2 JPS5931741B2 (en) 1984-08-03

Family

ID=15218515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53138294A Expired JPS5931741B2 (en) 1978-11-09 1978-11-09 Buffer block return control method

Country Status (1)

Country Link
JP (1) JPS5931741B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58171780A (en) * 1982-03-31 1983-10-08 Fujitsu Ltd Managing method of main storage
JPS6336348A (en) * 1986-07-30 1988-02-17 Toshiba Corp Buffer memory control method
JPH02161514A (en) * 1988-12-14 1990-06-21 Fujitsu Ltd Control processing system for idle storage block
JP2019136168A (en) * 2018-02-07 2019-08-22 株式会社平和 Game machine

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6026742U (en) * 1983-07-29 1985-02-23 株式会社東海理化電機製作所 Changeover switch device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58171780A (en) * 1982-03-31 1983-10-08 Fujitsu Ltd Managing method of main storage
JPH0131217B2 (en) * 1982-03-31 1989-06-23 Fujitsu Ltd
JPS6336348A (en) * 1986-07-30 1988-02-17 Toshiba Corp Buffer memory control method
JPH0517584B2 (en) * 1986-07-30 1993-03-09 Tokyo Shibaura Electric Co
JPH02161514A (en) * 1988-12-14 1990-06-21 Fujitsu Ltd Control processing system for idle storage block
JP2019136168A (en) * 2018-02-07 2019-08-22 株式会社平和 Game machine

Also Published As

Publication number Publication date
JPS5931741B2 (en) 1984-08-03

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