JPS5563838A - Preparation of semiconductor integrated circuit - Google Patents
Preparation of semiconductor integrated circuitInfo
- Publication number
- JPS5563838A JPS5563838A JP13732378A JP13732378A JPS5563838A JP S5563838 A JPS5563838 A JP S5563838A JP 13732378 A JP13732378 A JP 13732378A JP 13732378 A JP13732378 A JP 13732378A JP S5563838 A JPS5563838 A JP S5563838A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxidization
- type
- bipolar transistor
- coexistence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 4
- 230000003321 amplification Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 238000005121 nitriding Methods 0.000 abstract 1
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
PURPOSE:To enable the coexistence of a I<2>L (Integrated Injection Logic) and a bipolar transistor by conducting heat treatment for oxidization at temperatures that provide a different rate of oxidization due to the difference of concentration near the surface of semiconductor. CONSTITUTION:An n-type epitaxial layer 2 is grown on a p-type substrate 1 through an n<+> embedded layer 4, and then a dielectric 18 of oxide film or nitriding film on its surface is removed by etching. After masking it, n-type impurities are diffused up to the required depth to form a high concentration n-type layer 12. In the next step, if the temperature for thermal oxidization is lowered, the rate of oxidization in the layer 12 becomes more rapid than that of others. As the result, a step is formed on the surface thereof. Next, an oxide film 13 is removed, and then the high concentration n-type layer is dispersed through high temperature treatment at a time when the isolation and others are formed to lower the concentration near its surface, thereby forming the I<2>L and the bipolar transistor by means of conventional method. In this arrangement, the epitaxial layer of I<2>L becomes thinner to improve a current amplification factor thereof, whereas the high dielectric strength of the bipolar transistor can be maintained to enable the coexistence of them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13732378A JPS5563838A (en) | 1978-11-09 | 1978-11-09 | Preparation of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13732378A JPS5563838A (en) | 1978-11-09 | 1978-11-09 | Preparation of semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5563838A true JPS5563838A (en) | 1980-05-14 |
| JPS6131636B2 JPS6131636B2 (en) | 1986-07-21 |
Family
ID=15195984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13732378A Granted JPS5563838A (en) | 1978-11-09 | 1978-11-09 | Preparation of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5563838A (en) |
-
1978
- 1978-11-09 JP JP13732378A patent/JPS5563838A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6131636B2 (en) | 1986-07-21 |
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