JPS5563443A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5563443A
JPS5563443A JP13747978A JP13747978A JPS5563443A JP S5563443 A JPS5563443 A JP S5563443A JP 13747978 A JP13747978 A JP 13747978A JP 13747978 A JP13747978 A JP 13747978A JP S5563443 A JPS5563443 A JP S5563443A
Authority
JP
Japan
Prior art keywords
interruption
signal
shunt
stack
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13747978A
Other languages
Japanese (ja)
Inventor
Tomoji Nukiyama
Junichi Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13747978A priority Critical patent/JPS5563443A/en
Publication of JPS5563443A publication Critical patent/JPS5563443A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To detect the error due to the overflow of stack memory easily, by providing the detection means to detect the specific value represented in the stack counter, in the data processor having the stack area indicating the address shunt.
CONSTITUTION: The stack exclusive memory 1 having the shunt address permissible addresses of n sets writes in the shunt addresses A1WAi (where: i is the number of times of subroutine processing generation), when the interruption processing and subroutine processing are caused, by the number of times of production, and the counter 4 counts the number of times i. The number of times i is interpreted with the decoder 6 and when i=n+1, the detection signal B is produced. The logical judgement between the signal B and the interruption control signal A is made at the logic circuit 8 to produce the internal interruption signal with the internal interruption control circuit 9. Further, in case of the interruption shunt addresses IWK address from external, i=K is detected with the decoder 6 and the signal C is produced when the interruption from external is no more received, and it is fed to the external interruption control circuit 7.
COPYRIGHT: (C)1980,JPO&Japio
JP13747978A 1978-11-08 1978-11-08 Information processor Pending JPS5563443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13747978A JPS5563443A (en) 1978-11-08 1978-11-08 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13747978A JPS5563443A (en) 1978-11-08 1978-11-08 Information processor

Publications (1)

Publication Number Publication Date
JPS5563443A true JPS5563443A (en) 1980-05-13

Family

ID=15199579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13747978A Pending JPS5563443A (en) 1978-11-08 1978-11-08 Information processor

Country Status (1)

Country Link
JP (1) JPS5563443A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04128345U (en) * 1991-05-10 1992-11-24 カシオ計算機株式会社 signal processing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04128345U (en) * 1991-05-10 1992-11-24 カシオ計算機株式会社 signal processing device

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