JPS5557965A - Address converter - Google Patents
Address converterInfo
- Publication number
- JPS5557965A JPS5557965A JP16329878A JP16329878A JPS5557965A JP S5557965 A JPS5557965 A JP S5557965A JP 16329878 A JP16329878 A JP 16329878A JP 16329878 A JP16329878 A JP 16329878A JP S5557965 A JPS5557965 A JP S5557965A
- Authority
- JP
- Japan
- Prior art keywords
- address
- memory unit
- memory
- searched
- actual address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To realize an excellent associative memory for address conversion by combining a high-speed small memory with a low-speed mass memory.
CONSTITUTION: With 1st memory unit 100 stored with a couple of a virtual address and actual address, 2nd memory unit 105 is combined which is slower in access and larger in capacity than the 1st memory unit and when a virtual address to be searched reside in the 1st memory unit, a corresponding actual address is immediately outputted. When it resides in the 2nd memory unit 105, the virtual address to be searched and the corresponding actual address are written in the 1st memory unit and the actual address is outputted. In this way, an associative memory can be realized whose shortest time of address conversion time is short.
COPYRIGHT: (C)1980,JPO&Japio
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US86558477A | 1977-12-29 | 1977-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5557965A true JPS5557965A (en) | 1980-04-30 |
JPS5713946B2 JPS5713946B2 (en) | 1982-03-20 |
Family
ID=25345829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16329878A Granted JPS5557965A (en) | 1977-12-29 | 1978-12-27 | Address converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5557965A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0138675A2 (en) * | 1983-09-22 | 1985-04-24 | Digital Equipment Corporation | Virtual address mapping using a 2-level translation buffer |
-
1978
- 1978-12-27 JP JP16329878A patent/JPS5557965A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0138675A2 (en) * | 1983-09-22 | 1985-04-24 | Digital Equipment Corporation | Virtual address mapping using a 2-level translation buffer |
EP0138675A3 (en) * | 1983-09-22 | 1986-12-30 | Digital Equipment Corporation | Virtual address mapping using a 2-level translation buffer |
Also Published As
Publication number | Publication date |
---|---|
JPS5713946B2 (en) | 1982-03-20 |
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